After a third ADC card was added to the h1lsc0 I/O chassis (alog 7842), I edited the h1lsc model as follows:
- added a DAC part and a third ADC part
- a few ADC/DAC channels were added or rewired according to T1100472-v10
- and a few ALS parts were added or renamed accordingly
- ALS-C_REFL_DC_ERR is now summed into the LSC input matrix
- added Beckhoff communication link (grounded for now)
- added iscex IPCs
- updated IMC and PSL blocks to match LLO (the LSC block is still divergent)
The new model has been compiled, started, and checked into SVN. Its MEDM overview, safe.snap and filter files will be updated and checked in tomorrow.
MEDM screens, filter file, and safe.snap have been updated and checked in. The filters from ALS_C_COMM_A_RF_I were moved to ALS_C_COMM_A_RF_ERR. More details about the rewiring:
- MCREFL was moved from adc_0_28 to adc_2_0
- All ALS inputs except DIFF_LF and COMM_LF are now on the new ADC (previously only one of them was connected, on adc_0_29)
The reflective memory links between h1lsc and h1iscex were not working, because the card number parameter of the cdsIPCx_RFM parts was wrong. I had just copy-pasted the parts from EY to EX and forgot to change this parameter. For the record, the correct card number settings are: "0" for EX and "1" for EY. After the h1lsc and h1iscex models were updated to get this right, the RFM links came up. The updated models have been checked in to SVN.