[Dave, Erik]
Dave found that DACs in h1sush2a were in a FIFO HIQTR state since 2024-04-09 11:33 UTC.
FIFO HIQTR means that DAC buffers had more data than expected. DAC latency would be proportionally higher than expected.
The models were restarted, which fixed the issue.
The upper bound on sush2a latency for the first three months of O4B is 39 IOP
cycles. At 2^16 cycles per second, that's a maximum of 595
microseconds.
At 1 kHz that's 214 degrees of phase shift.
Normal latency is 3 IOP cycles, 46 microseconds, 16 degrees phase shift
@ 1 kHz.
The minimum latency when sush2a was in error was 4 cycles, 61
microseconds, 23 deg @ 1 KHz.