erik.vonreis@LIGO.ORG - posted 08:44, Wednesday 03 July 2024 - last comment - 11:16, Wednesday 03 July 2024(78827)
h1sush2b had timing glitch caused by h1sush2a DAC replacement
At 14:44 UTC h1sush2b suffered a timing error and had to be restarted.
The timing error happened when work was being done in the same rack in the CER, see https://alog.ligo-wa.caltech.edu/aLOG/index.php?callRep=78823.
The timing error was a "long cycle" of 50 milliseconds.
Restart log for this morning's work:
Wed03Jul2024
LOC TIME HOSTNAME MODEL/REBOOT
05:30:57 h1sush2a ***REBOOT***
05:33:09 h1sush2a h1iopsush2a
06:45:01 h1sush2a ***REBOOT***
06:47:12 h1sush2a h1iopsush2a
07:18:01 h1sush2a ***REBOOT***
07:20:13 h1sush2a h1iopsush2a
07:35:51 h1sush2a ***REBOOT***
07:38:04 h1sush2a h1iopsush2a
07:38:17 h1sush2a h1susmc1
07:38:30 h1sush2a h1susmc3
07:38:43 h1sush2a h1susprm
07:38:56 h1sush2a h1suspr3
07:59:25 h1sush2b ***REBOOT***
08:01:07 h1sush2b h1iopsush2b
08:01:20 h1sush2b h1susim
08:01:33 h1sush2b h1sushtts