J. Kissel, with help from E. von Reis, D. Barker, D. Sigg
WP 11969

Continuing investigations of high frequency limitations of characterizing the anti-aliasing processing performance for the 524 kHz OMC DCPD system (LHO:78516), there are a few unconfirmed suspicions about whether the flat noise "limit" above ~20 kHz -- seen in only in the NOMINAL_LOW_NOISE data -- is ADC noise or numerical precision issues. There are two suggested measurements that would confirm one or the other empirically:
   (1) "Compare the high frequency noise of 4 channel sum / average against the noise in a single channel"
        If the noise changes by sqrt(4) = 2 (with the underlying assumption that the noise of the ADC is identical for each channel), then the noise floor is ADC noise not precision limit.
   (2) "High pass the data in the real-time to remove the large DC component"
        If the low frequency DC signal is removed in the real time system -- which is running at 32-bit double precision, and *then* we compute the ASD via a grabbing the data once turned into a test point (which is done at single precision) -- then the ASD should *not* be limited by the single precision noise floor.

However, the current infrastructure doesn't support either tests.
   For (1), while we do have access to the the ADC channels are summed immediately off the ADC as test points (i.e. H1:IOP-OMC0_MADC0_CH[0,4,8,12]), they're not piped into any filter banks, so we can't make any of the high-dynamic-range testing of the Digital AA filtering comparisons with the output of the primary DCPD banks.
   For (2), these are the gravitational wave channels, and the in-loop DARM loop error signals. "Just toss in a high-pass" is not an option (the DARM loop would go unstable and/or at least lose a bunch of low frequency gain; if if the IFO would funciton it would mean drastic impact on the calibration of the detector).

As such, I'm document here the front-end model changes I hope to install that creates pick-off paths for the eight ADC channels (four copies of the voltage from DCPD A and four for DCPD B), piping them in to an ADC_INMTRX matrix (along with the 4 channel sum) for a total of 10 inputs, and then piping that output of that matrix into 4 filter banks whose output is terminated. The design intent is for these filter banks to mostly contain exact copies of the primary DCPD_A0 and B0 filter banks, but we're free to modify them and play around with, say, adding a high pass, whenever we want without consequences for the detector. I'm also a big fan of "clean as you go," so I've also taken the opportunity to make the simulink diagram a (little cleaner / legible / less redundant) for the primary existing paths.
 
Attached are screenshots showing the model changes:
    - Top level before vs. after
        Comparing these two, you see immediately the new input matrix. But also, you see that the PI path is now no longer a equal parallel copy of the sum of the channels, but instead the sum is done once, and the output of the sum is fed into the OMC block to be split out in there.
    - One layer down, into the top_named OMC block, before vs. after
        Here is where the OMC DCPD 4 channel sum is picked off for the PI path with a goto tag, rather than re-computing the sum. The new matrix output channels are fed into the DCPD block.
    - A further layer deeper, into the OMC_DCPD block, before vs. after
        Here the new matrix output channels are fed into 4 filter banks.

At the moment, we're unsure whether the 524 kHz system can handle this many more filter banks without running out of computation time to ship the PI data to the end stations. So we may end up reducing the amount of test filters from 4 to 2. Further, once we gather enough data, there may be a chance that we no longer need these test pickoff filters. Thus, at the moment, this a "prototype" change, with work permit only, and not an ECR -- since it may not be needed for more that a week or two.