J. Kissel, E. von Reis, D. Sigg Circa March 2023, Daniel had installed some never-used first attempts at further filtering the high frequency noise present in the 524 kHz OMC DCPD channels (never aLOGged because it was never used, but I call them out after I found the work in LHO:68098). Now, because I'd like to characterize the existing, in-use, digital AA filtering, running into some unknown noise (LHO:78516), and hoping to install 2 to 4 more parallel filter banks that would also be quite full of filters (LHO:78956), there is worry that there won't be enough computation time in the 524 kHz system. Remember, that "the 524 kHz system" is actually a modified "standard" 65 kHz system, which is reading out 8 samples from the 524 kHz ADC each 65 kHz clock cycle and computing everything at 65 kHz. Thus, in principle, the max turn around time is 1 / (2^16 Hz) = (1 / 65536) [sec] = 1.5258789e-5 [sec] = 15.3 [usec] However, we *think* the practical limit is somewhat less that this. I don't think I understand what those limitations are enough to say definitively and/or to quote a limit quantitatively, but I think they're related to "the copy of the OMC DCPD channels which are demodulated at high frequency to create PI channels that are shipped to the end station -- in other words, the IPC sending demands a bit of computational time, and if there isn't enough turnaround time left in the OP to write to the IPC network, then the end-station SUS PI models throw an IPC timing error." Anyways -- this morning, I looked at the 524 kHz system's computation time as is before doing anything (via the channel H1:FEC-179_CPU_METER), and it's sitting at 9 [usec] (out of the ideal 15 [usec]), occasionally popping up to 10 [usec]. But -- this led me to remember that -- regardless of whether the filter is turned ON -- the front-end computes the output of the filter -- sucking up computation time. So, I've removed these unused prototype notch filters from the DCPD A0 and B0 filter banks. In addition, I've also removed the old "V2A" filter from a previous version of the digital compensation for the OMC DCPD transimpedance amplifier response. Removing the notch filters drops the computation time from "9 [sec] occasionally bopping up to 10 [usec]." See attached time series of the CPU meter. These filters are, of course, available in the filter_archive, under the latest previous archived file before today's work: /opt/rtcds/lho/h1/chans/filter_archive/h1iopomc0/ H1IOPOMC0_1401558760.txt but for ease of use, I copy them here. FM3 :: Notches1 ellip("BandStop",3,0.5,30,12800,13200) notch(10216,50,30) ellip("BandStop",3,0.5,30,10380,10465) ellip("BandStop",3,0.5,30,12900,13100) FM5 :: Notches2 ellip("BandStop",3,0.5,30,8100,8200) notch(9101,50,30)notch(9337,200,30) notch(9463,50,20) ellip("BandStop",3,0.5,30,9750,9950) FM8 :: Notches3 ellip("BandStop",5,0.5,40,14384,18384) ellip("BandStop",5,0.5,40,30768,34768) FM6 :: V2A zpk([5.699+i*22.223;5.699-i*22.223;32.73],[2.549;2.117;6.555],0.00501187,"n")gain(0.971763) I've also posted a plot of the magnitude of these notch filters -- mostly just to demonstrate how many second order sections that these filters had -- sucking up computation time.
Keita, Sheila
We were looking for explanations for the drops in range we've seen since Tuesday. Attached is a plot of the CPU meter, it seems that this jumped up shortly after Jeff's plot was made. It is still below 13usec, and doesn't look correlated with our range problems.
Variation of CPU time in that range shouldn't by itself have any effect on the control loops running on that model until they get to a sustained time above 15 us or an individual cycle time somewhat more than 15 us depending on the model.
The effects of a model that's run too long are DAC buffer starvation, i.e. the IOP didn't keep up with the DAC clocks, or IPC communication between models arriving to late.
Both of these errors would appear immediately on the CDS overview MEDM.