J. Kissel, A. Pele, C. Wipf, S. Dwyer

In hopes to further progress towards a speedy recovery from a power failure, we have done the following:
(1) Captured and committed the following safe.snap files:
${userapps}/release/sus/h1/burtfiles/h1susmc1_safe.snap
${userapps}/release/sus/h1/burtfiles/h1susmc2_safe.snap
${userapps}/release/sus/h1/burtfiles/h1susmc3_safe.snap
${userapps}/release/sus/h1/burtfiles/h1susim_safe.snap

${userapps}/release/asc/h1/burtfiles/h1ascimc_safe.snap

${userapps}/release/lsc/h1/burtfiles/h1lsc_safe.snap

(2) ensured that all relevant safe.snaps in the target directory are soft links to the userapps repo
/opt/rtcds/lho/h1/target/h1susmc1/h1susmc1epics/burt/safe.snap -> /opt/rtcds/userapps/release/sus/h1/burtfiles/h1susmc1_safe.snap
/opt/rtcds/lho/h1/target/h1susmc2/h1susmc2epics/burt/safe.snap -> /opt/rtcds/userapps/release/sus/h1/burtfiles/h1susmc2_safe.snap
/opt/rtcds/lho/h1/target/h1susmc3/h1susmc3epics/burt/safe.snap -> /opt/rtcds/userapps/release/sus/h1/burtfiles/h1susmc3_safe.snap
/opt/rtcds/lho/h1/target/h1susim/h1susimepics/burt/safe.snap -> /opt/rtcds/userapps/release/sus/h1/burtfiles/h1susim_safe.snap

/opt/rtcds/lho/h1/target/h1ascimc/h1ascimcepics/burt/safe.snap -> /opt/rtcds/userapps/release/asc/h1/burtfiles/h1ascimc_safe.snap  ## This one wasn't a soft link before now 

/opt/rtcds/lho/h1/target/h1lsc/h1lscepics/burt/safe.snap -> /opt/rtcds/userapps/release/lsc/h1/burtfiles/h1lsc_safe.snap
(3) edited MClockwatch code to ensure that the ASC outputs on all stages of each IMC optic (H1:SUS-MC[1,2,3]_M[1,2,3]_LOCK_[P,Y]), and the the lowest stage LSC output on MC2 (H1:SUS-MC2_M3_LOCK_L) are turned ON in the "unlocked" portion of 
/opt/rtcds/userapps/release/ioo/h1/scripts/imc/sballmer/MClockwatch
which are now the only LOCK settings that are different between the SAFE state and the READY state.

Note, in absence of the transitions between SAFE and READY, the user still has to turn on the MASTERSWITCH (to get to DAMPED) and the OPTICALIGN alignment offsets (to get to ALIGNED) for MC1, MC2, and MC3. Simply starting the MClockwatch script will then transition MC2 to its READY state, and begin to try and lock the mode cleaner. Remember that turning on the ASCIMC control is now triggered by the front end, so as long as its settings are properly restored on startup (which the above three steps should now ensure), the user and MClockwatch script should not have to worry about it.