Per WP12079 we started measurements to compare directly the 20 bit DAC driving the ESD and L3 to our LD32. 

Comparing ESD Driving Signals
Test 1 - LD32 bank 1 (ch 0-7) attached to 0-7 on the PEM ADC ; 20 bit DAC ESD signal attached to 8-15 on the PEM ADC

Comparing L3 Driving Signals
Test 2 - 20 bit DAC L3 attached to 0-7 PEM ADC : LD32 bank 2 (ch 8-15) attached to 8-15 on the PEM ADC

After analysis of the data, we measured about ~14us delay in the LD32 which is accounted for by the Anti Imaging filter on the FPGA.  We also determined the gain should be ~275.65 to achieve the same calibration between both DACs.

Driving the ESD and L3 with the LD32 will be postponed until next week.

daniel sigg, dave barker, marc pirello