daniel.sigg@LIGO.ORG - posted 16:15, Tuesday 10 September 2024 - last comment - 15:53, Thursday 12 September 2024(80023)
New DAC gain and delay measurements
Marc Daniel
We measured the gain and phase difference between the new DAC and the existing 20-bit DAC in SUS ETMX. For this we injected 1kHz sine waves and measure gain and phase shifts between the two. We started with a digital gain value of 275.65 for the new DAC and adjusted it to 275.31 after the measurement to keep the gains identical. The new DAC implements a digital AI filter that has a gain of 1.00074 and a phase of -5.48° at 1kHz, which corresponds to a delay of 15.2µs.
This puts the relative gain (new/old) to 1.00074±0.00125 and the delay to 13.71±0.66µs. The variations can be due to the gain variations in the LIGO DAC, the 20-bit DAC, the ADC or the AA chassis.
| DAC | Channel Name | Gain | Adjusted | Diff (%) | Phase (°) | Delay (us) |
| 0 | H1:SUS-ETMX_L3_ESD_DC | 1.00239 | 1.00114 | 0.11% | -5.29955 | -14.72 |
| 1 | H1:SUS-ETMX_L3_ESD_UR | 1.00026 | 0.99901 | -0.10% | -5.10734 | -14.19 |
| 2 | H1:SUS-ETMX_L3_ESD_LR | 1.00000 | 0.99875 | -0.12% | -4.93122 | -13.70 |
| 3 | H1:SUS-ETMX_L3_ESD_UL | 1.00103 | 0.99978 | -0.02% | -5.11118 | -14.20 |
| 4 | H1:SUS-ETMX_L3_ESD_LL | 1.00088 | 0.99963 | -0.04% | -5.21524 | -14.49 |
| 8 | H1:SUS-ETMX_L1_COIL_UL | 1.00400 | 1.00275 | 0.27% | -4.72888 | -13.14 |
| 9 | H1:SUS-ETMX_L1_COIL_LL | 1.00295 | 1.00170 | 0.17% | -4.88883 | -13.58 |
| 10 | H1:SUS-ETMX_L1_COIL_UR | 1.00125 | 1.00000 | 0.00% | -5.08727 | -14.13 |
| 11 | H1:SUS-ETMX_L1_COIL_LR | 1.00224 | 1.00099 | 0.10% | -4.92882 | -13.69 |
| 12 | H1:SUS-ETMX_L2_COIL_UL | 1.00325 | 1.00200 | 0.20% | -4.78859 | -13.30 |
| 13 | H1:SUS-ETMX_L2_COIL_LL | 1.00245 | 1.00120 | 0.12% | -4.55283 | -12.65 |
| 14 | H1:SUS-ETMX_L2_COIL_UR | 1.00175 | 1.00050 | 0.05% | -4.52503 | -12.57 |
| 15 | H1:SUS-ETMX_L2_COIL_LR | 1.00344 | 1.00219 | 0.22% | -5.00466 | -13.90 |
| Average | 1.00199 | 1.00074 | 0.07% | -4.93611 | -13.71 | |
| Standard Deviation | 0.00125 | 0.00125 | 0.13% | 0.23812 | 0.66 |
FPGA filter is
zpk([585.714+i*32794.8;585.714-i*32794.8;1489.45+i*65519.1;1489.45-i*65519.1;3276.8+i*131031; \
3276.8-i*131031;8738.13+i*261998;8738.13-i*261998], \
[11555.6+i*17294.8;11555.6-i*17294.8;2061.54+i*26720.6;2061.54-i*26720.6;75000+i*93675; \
75000-i*93675;150000+i*187350;150000-i*187350;40000],1,"n")