D. Barker, E. Dohmen, J. Kissel

As a result of the failure of h1susb123's DAC_1, card_num = 1 (with counting starting at 0), in Slot 4 of the IO chassis which drives ITMX and ITMY's reaction chain R0 F1F2F3SD OSEMs (see LHO:84500 and call-out of the card in this screenshot of D1301004-v4) we've agreed to "just" upgrade the entire chassis to 20-bit DACs per E1900216 (IIET:13232).

After a careful review of the user model layout of this very confusing mixed IO chassis -- with DAC cards shared across suspensions coupled with an barely intuitive order of which stage is assigned to which card -- Dave, EJ, and I have confirmed that the following AFTER screetshots show the correct DAC (re)assignments for upgrading the entire h1susb123 chassis to 20 bit DACs. 
    - h1susitmy BEFORE vs AFTER
    - h1susitmx BEFORE vs AFTER
    - h1susbs BEFORE vs. AFTER, and
    - h1susitmpi BEFORE vs. AFTER.

I also attach the BEFORE as-built card layout from D1301004-v4, and the "this is the truth" map of which stage uses what card from the redlines written in the abstract of D1100022-v13.

These models are ready for install and have been committed to
    /opt/rtcds/userapps/release/sus/h1/models/
        h1susbs.mdl
        h1susitmpi.mdl
        h1susitmx.mdl
        h1susitmy.mdl

as of userapps svn repo version 31490.