F. Clara, J. Figueroa, J. Kissel, M. Pirello ECR E2400409 and E2500296 (IIET 35739 and 35706, respectively) WP 12901 DWG D0902810-v12 DCN E2500341 Today we've gone forward with merging the sush2a and sush2b IO chassis, facilitated by upgrading those SUS's DAC cards to 32 CH, 28- bit DACs (D2200368). This entry covers the analog electronics and cabling that were impacted by the change, covering that all of the suspensions in, or soon to be in HAM1 and HAM2 -- MC1, MC3, PRM, PR3, IM1, IM2, IM3, IM4, RM1, RM2, PM1, JM1, and JM3. We followed changes outlined in E2500341 which highlights the changes in the sush12 SUS electronics system drawing from D0902810-v11 to D0902810-v12. That required - disconnecting all affected AI output cables in SUS-C3 and SUS-C4, - Removing the existing 6x 2x 8CH DAC AI chassis (D1000305), - modifying them to become D2500353 1x 32CH AI chassis . replacing the 2x 8CH AI rear panel with WD relays (D1000551) with 1x 32CH AI rear panel without WD relays (D2500097) . replacing the 2x 8CH back panel (https://dcc.ligo.org/LIGO-D1000552 with 1x 32CH back panel (D2400308) - re-installing, then - cabling everything up according to the D0902810-v12 version of the wiring diagram. Here's the list of modified AI chassis serial numbers and assignment: D1000305 > D2500353 D2500097 SUS Chain Rack / Position Chassis S/N Rear Board S/N 32CH DAC Card / IO Slot Channels (Counting from 0) MC1, MC3, PRM TOPs SUS-C4 / U30 S1104370 S2501311 DAC0 / #2 0-15 PRM, PR3 TOPs MC1 MID BOT SUS-C4 / U29 S1104374 S2501315 DAC0 / #2 16-31 MC3, PRM MID/BOT SUS-C4 / U22 S1104375 S2501310 DAC1 / #4 0-15 PR3 MID/BOT, RM1, RM2 SUS-C4 / U21 S1104378 S2501312 DAC1 / #4 16-31 IM1, IM2, IM3, IM4 SUS-C4 / U10 S1104377 S2501314 DAC2 / #5 0-15 PM1, JM1, and JM3 SUS-C4 / U2 S1102760** S2501313 DAC2 / #5 16-31 ** Technically, the (now) PM1, JM1, and JM3 AI chassis S1102760 was a 16-bit DAC AI chassis (D1101521) instead of a D1000305 at the start of today, and it didn't *need* the additional 16CH pass-through SCSI connection, but in the spirit of making everything the same, we elected to make it a full "new normal" D2500353 chassis.
Updated H1-SUSH12 Timing FPGA code to latest firmware version 1589 V5
Updated H1-SUSH2AUX timing FPGA code to latest firmware version 1589 V5
Rebooted both chassis and they are now reporting correctly according to Dave.
For reference: The 16-chn/16-bit AI chassis with interface boards D070101 are not compatible with the new 32-chn DACs. Both have a 68-pin SCSI connector but the pinout isn't compatible.