Adding CHETA slow controls channels to DAQ EDC
Jonathan, Erik, Dave:
Following the installation of the CHETA Beckhoff chassis in the Vacuum Prep Lab we added the 724 AWC channels for itm[x,y] to H1EPICS_ECATTCSCS.ini for inclusion into the EDC.
at 12:22 I did a DAQ 1-leg and EDC restart. The EDC would not run, its systemd service was in a continual respawn state.
The number of EDC channels had increased from 59894 to 60618, and I remembered that there is a channel limit in the EDC code, which Erik verified was 60k.
Erik quickly built a new EDC with a 70k limit and installed this on h1susauxh56.
In the mean time I had put the H1EDC.ini file back and restarted 1-leg and EDC to get everything stable again.
At 13:22 we did a second round of DAQ+EDC restarts with the expanded channel list which was successful.
Installing h1sush6 IO Chassis
Fil, Dave, Erik:
I relocated the old h1sush2b IO Chassis from the CER to the MER. It is in the bottom of the SUS-HAM6 rack, at the same height as the neigboring h1sush7 and h1seih7.
I pulled a new MTP fiber from the IO Chassis to the MER patch panel, using the third port.
This IO Chassis currently has the cards left over after the h1sush2[a,b] consolidation in Dec 2025, we will populate it with the correct cards later.
Current layout:
| A1-1 | LIGO Timing Card | A3-1 | ||
| A1-2 | A3-2 | |||
| A1-3 | A3-3 | |||
| A1-4 | ADC-0 | A3-4 | ||
| A2-1 | 16bit-DAC-0 | A4-1 | Contec6464 BIO-0 | |
| A2-2 | 16bit-DAC-1 | A4-2 | ||
| A2-3 | A4-3 | |||
| A2-4 | A4-4 |
No work was done on the front end computer in the MSR.
Later this week when the IO Chassis is powered up we will make the following changes in the MSR to the old h1susb2b computer:
1. disconnect the Dolphin cable from its IX card and verify the Dolphin switch port is fenced
2. move the MTP from the CER patch over to the 3rd port on the MER patch
3. run puppet to reconfigure the boot server to boot this computer as h1sush6 sans-Dolphin and only running h1iopsush5 model
4. boot the computer and verify the IO Chassis can be seen, the IOP runs and that the timing is good.
Tue24Feb2026
LOC TIME HOSTNAME MODEL/REBOOT
12:22:50 h1daqdc1 [DAQ] <<< First try of 1-leg + EDC restart
12:23:00 h1daqfw1 [DAQ]
12:23:01 h1daqtw1 [DAQ]
12:23:04 h1daqnds1 [DAQ]
12:23:09 h1daqgds1 [DAQ]
12:27:09 h1daqgds1 [DAQ] (GDS1 needed a restart)
12:27:39 h1susauxh56 ***REBOOT*** <<< EDC wont start, tried a reboot
12:28:38 h1susauxh56 h1iopsusauxh56
12:28:51 h1susauxh56 h1susauxh56
12:33:33 h1susauxh56 h1edc[DAQ] <<< backed out EDC chan change, restarted EDC+1-leg
12:34:32 h1daqdc1 [DAQ]
12:34:44 h1daqfw1 [DAQ]
12:34:44 h1daqtw1 [DAQ]
12:34:45 h1daqnds1 [DAQ]
12:34:52 h1daqgds1 [DAQ]
12:35:32 h1daqgds1 [DAQ] (GDS1 needed a restart)
13:22:31 h1daqdc1 [DAQ] <<< Restart 1-leg + EDC with new code and new chans
13:22:44 h1daqfw1 [DAQ]
13:22:45 h1daqtw1 [DAQ]
13:22:48 h1daqnds1 [DAQ]
13:22:54 h1daqgds1 [DAQ]
13:24:13 h1susauxh56 h1edc[DAQ]
13:31:12 h1daqgds0 [DAQ] <<< Restart 0-leg
13:31:19 h1daqfw0 [DAQ]
13:31:19 h1daqtw0 [DAQ]
13:31:20 h1daqnds0 [DAQ]
13:31:40 h1daqfw1 [DAQ] <<< FW1 spontaneous restart