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Reports until 16:29, Wednesday 08 April 2026
H1 CDS
david.barker@LIGO.ORG - posted 16:29, Wednesday 08 April 2026 - last comment - 16:57, Wednesday 08 April 2026(89832)
CDS Maintenance Summary: Wednesday 8th April 2026

WP13110 IO Chassis Timing Card Firmware and Sync Ribbon Upgrade

Marc, Erik, Dave:

The timing card sync ribbon cable and the timing card firmware were upgraded on the following front ends

front end firmware ribbon models built RCG5.5.2
h1omc0 already done yes all [h1iopomc0, h1omc, h1omcpi]
h1lsc0 yes yes already done
h1oaf0 yes yes already done
h1asc0 yes yes already done

Corner Station BSC ISI GND STS shuffle

Jim, Erik, EJ, Dave:

The 9 GND STS channels (X,Y,Z for A,B,C) were being read by h1isiitmy and sent to seiproc via 9 PCIE IPC channels.

Today's change was to reduce those handled by h1isiitmy to the "A" set of three. Add the "B" set to h1isibs and the "C" set to h1isiitmx.

IPC senders have TX slow channels in the INI file, so a DAQ restart was required to remove the "BC" channels from itmy and add them to bs and itmx.

We chose to not change the name of the IPC channels, they remain H1:ISI-ITMY_[A,B,C]_GND_[X,Y,Z]_IPC_PCIE. Technically they are incorrect for those on BS and ITMX since they retain their ITMY designator.

Keeping the ITMY names meant we did not have to remove channels from the H1.ipc file. That being said, this file did need a hand edit to change the sending model/frontend for the channels which moved to bs, itmx. This was needed so these models could build without RCG reporting "channel already exists on another model".

After h1isi[itmy, bs, itmx] were restarted with the new code, the DAQ was restarted (no EDC restart).

Jim then found that the signals for the new IPC channels were not correct, for example h1isibs was sending the wrong ADC signals, the ADC channel numbers were offset by 3.

We tracked this down to a problem with the bus-creator -> goto-tag -> ADC-bus_selector chain between the ADC selector and the IPC parts. Jim cleaned this up by replacing all of this with 3 goto-tags for the X, Y and Z channels.

After a second round of model restarts I verified the correct ADC channels were being read and sent to h1seiproc.

Comments related to this report
david.barker@LIGO.ORG - 16:57, Wednesday 08 April 2026 (89833)

Wed08Apr2026
LOC TIME HOSTNAME     MODEL/REBOOT
10:08:13 h1omc0       ***REBOOT*** <<< Timing Card Upgrades
10:09:39 h1omc0       h1iopomc0   
10:09:52 h1omc0       h1omc       
10:10:05 h1omc0       h1omcpi     
10:27:06 h1lsc0       ***REBOOT***
10:28:44 h1lsc0       h1ioplsc0   
10:28:57 h1lsc0       h1lsc       
10:29:10 h1lsc0       h1lscaux    
10:29:23 h1lsc0       h1sqz       
10:29:36 h1lsc0       h1ascsqzfc  
10:38:53 h1oaf0       ***REBOOT***
10:40:36 h1oaf0       h1iopoaf0   
10:40:49 h1oaf0       h1pemcs     
10:41:02 h1oaf0       h1tcscs     
10:41:15 h1oaf0       h1susprocpi 
10:41:28 h1oaf0       h1seiproc   
10:41:41 h1oaf0       h1oaf       
10:41:54 h1oaf0       h1calcs     
10:42:07 h1oaf0       h1susproc   
10:42:20 h1oaf0       h1calinj    
10:42:33 h1oaf0       h1bos       
11:51:23 h1asc0       ***REBOOT***
11:52:59 h1asc0       h1iopasc0   
11:53:12 h1asc0       h1asc       
11:53:25 h1asc0       h1ascimc    
11:53:38 h1asc0       h1ascsqzifo 


12:12:12 h1seib1      h1isiitmy   <<< First round of new ISI models
12:12:42 h1seib2      h1isibs     
12:13:10 h1seib3      h1isiitmx   


12:15:44 h1daqdc1     [DAQ] <<< DAQ restarts for ISI models
12:15:54 h1daqfw1     [DAQ]
12:15:55 h1daqtw1     [DAQ]
12:15:59 h1daqnds1    [DAQ]
12:16:04 h1daqgds1    [DAQ]
12:17:31 h1daqgds1    [DAQ] <<< GDS1 second restart needed
12:21:08 h1daqgds0    [DAQ]
12:21:16 h1daqfw0     [DAQ]
12:21:16 h1daqnds0    [DAQ]
12:21:16 h1daqtw0     [DAQ]


13:22:13 h1seib1      h1isiitmy   <<< Second round of new ISI models with new IPC channels corrected
13:22:37 h1seib2      h1isibs     
13:23:02 h1seib3      h1isiitmx   
 

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