Per WP 13204 we added fw2 channels to the edc to save some frame writing information for the review of the new frame writer.

The usuall process was used:

1. regenerate the edc ini file

2. restart daq1 leg

3. restart the edc

4. restart daq0 leg

The daq1 leg was restarted around 8:20am localtime, followed by the edc.

The daq0 leg was restarted around 8:27am localtime.

There have been two restarts of h1daqfw0 since then, at 8:32 and 8:37.  Logs show that it was due to missing a input cycle (8:32) and running out of buffers in the circular buffer (8:37).  It as come back and appears to be stable now.