The new RCG separates the ADC and DAC overflow counters (previous RCGs combined them into a single counter). I have modifed the CDS Overview to show any model whose DAC counters are overflowing (counter > 0). This is shown as a purple square in the 6th block.  I have also added an overflow counter reset button in the lower right corner, called "OVRFLO RST", which issues an overflow reset on all models. Note that the overflow reset button resets both the ADC and the DAC counters.

Two models have continuous DAC overflows: h1tcscs and h1alsex. These are DC drives of 16bit-DAC channels

h1alsex

is driving its DAC ch8 (H1:ALS-X_WFS_AUTOC_PZT1_PIT_MON) with a dc signal of 35000, which exceeds the 16bit-DAC max value of 32768 before any upsampling.

h1tcscs

is driving its first 3 DAC chans each with a signal of 32768, which exceeds the operational range.

and is driving its DAC ch12 with a dc signal of 28521, which looks like it is in range, but after upsampling with zero-padding, produces an AC signal which spikes above 32k 2048 times per second.

We are investigating if we could change h1tcscs to no use zero-padding for its DAC. The main risks are with any non-DC drives, and possible recalibration for DC drives when they become actual DC signals.