WP13584,13585 Add 7th ADC to h1oaf0 IO Chassis, add to models
Erik, EJ, Jonathan, Fil, Dave:
A 7th ADC was added to h1oaf0's IO Chassis. Because all the cards in this chassis had been shifted left by one slot to move the 20bit-DAC from A1-4 to A2-1, there was only one slot ADC6 could go into, A3-4.
Erik and EJ took the opportunity of powering h1oaf0 to check the BIOS settings (some needed changing), performing Adnaco benchmark tests, and disconnecting A4 from the computer.
Fil installed the new AA chassis for ADC6, it currently does not have anything connected to its inputs.
Dave made h1iopoaf0 and h1pemcs model changes. PEM reads out all 32 channels of ADC6 into filtermodules H1:PEM-CS_ADC_6_[0-31]. These FMs have been turned on.
DAQ restart was required for the model changes.
WP13591 h1susbs add M3 matrix
Sheila, Ellena, Dave
A new h1susbs model was installed. A DAQ restart was required
WP13592 h1crsproc add BLRMS
Jim, Erik, EJ, Dave
A new h1crsproc model was installed. A DAQ restart was required
Note that the svn server redoubt was not available for a rev-lock build, so we did a "old fashioned" install
> rtcds build h1crsproc
> INSTALL_ONLY_REV_LOCKED=false rtcds install h1crsproc
DAQ Restart
Jonathan, Dave:
After the round of model restarts the DAQ was restarted; 0-leg followed by 1-leg. No EDC restart was required.
All framewriters rode through the restarts with no issues.
BIOS setting changed, now matching the LIGO-T1300430 document:
CPU C State Control :
Enhanced Halt State (C1E) : Enabled -> Disabled
Package C State Control:
Package C State : Auto -> C0/C1 state
We noted that h1oaf0's 6th ADC (ADC5) had failed its AUTOCAL. Trending shows this has been the case for at least 9 months.