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Reports until 22:19, Tuesday 09 February 2016
H1 ISC (ISC)
jenne.driggers@LIGO.ORG - posted 22:19, Tuesday 09 February 2016 - last comment - 08:48, Wednesday 10 February 2016(25480)
Something wrong with DARM loop

I'm not sure if the ESD changes today (alog 25468) are at fault, or if something else has changed today, but I cannot lock ALS Diff using the nominal loop. 

In order to lock ALS Diff, I have included a gain of 0.001 in the DARM2 filter bank (usually just has gain of 1, no filters yet).  Also, I have commented out the line in the Diff guardian that turns on DARM1 filters 2 and 3 (an integrator and resG respectively).  I can turn the DARM2 gain up to 0.002 or 0.004 most of the time, but at 0.006 the DARM loop starts to ring up over 2-3 seconds until we saturate the ETMX L3 coils.  Even at the very lowest teensy-tiny gain, I can't turn on either the integrator or the resG. 

There is so very little gain here that I can't measure the DARM loop in the 10-100 Hz band. 

Unsurprisingly, this means that Diff is too noisy to hold the Yarm anywhere in particular, so I can't move on with the locking sequence (with the thought that it would all be okay if I could get far enough to transfer to RF DARM). 

I am reverting my changes (uncommenting line 228 in ALS diff guardian and gain to 1 for DARM2 bank).

 

I'm calling it a night since I'm running low on ideas.

Also, Kiwamu straightened me out about the DARM filter module screen situation - the auto-generated screens live in the OMC folder.  He'll fix the overview screen tomorrow.

Comments related to this report
daniel.sigg@LIGO.ORG - 05:13, Wednesday 10 February 2016 (25482)

One should check for high frequency saturations. The ALS DIFF signal is fairly noisy and with the new wide bandwidth ESD we might have too much noise at ~kHz..

evan.hall@LIGO.ORG - 06:42, Wednesday 10 February 2016 (25483)

The digital compensation logic for the high-range ESD state is not correct.

In the high range state, the low-noise path is disconnected by a switch, so the analog PI RC network does not enter the overall TF of the driver. Therefore, we do not need to compensate its p/z pair (now 3.2 kHz / 67 kHz). However, the digital logic will still engage this p/z compensation unless you manually disable it (i.e., turn off the antiAcq filter in the ESD SFMs).

Turning off this filter allows DIFF to lock.

During the run, we ran with the binary I/O logic disabled (state request = −1), and the antiAcq filter off. This was changed during maintenance day on 19 Jan, after which point we were incorrectly compensating for this nonexistent p/z pair. This probably also explains the continual EX saturations that appeared during DRMI locking a few weeks ago.

keita.kawabe@LIGO.ORG - 08:48, Wednesday 10 February 2016 (25485)

It should have been digital sign flip.

Old filter was also incorrect in EX and was much more aggressive than the new one, so the HV driver saturation is not the reason that the IFO didn't lock.

The real issue is, when I changed the number of poles (from 1 to none because it went too high due to the hardware change), the sign of the digital TF unintentionally flipped. It's hard to read the sign flip by just looking at the gain-normalized zpk expression in foton (i.e. "n (Hz/norm)"), you need to look at something else e.g. "s" or "f" expression or the bode diagram:

Old one: zpk([152], [3250], 1, "n") in Hz/norm = zpk([-955], [-20420], 21.38) in s (red in the attached)

New one: zpk([3225, [], 1, "n") in Hz/norm = zpk([-20263.27], [-32768], -1.617) in s (blue in the attached)

This of course applies to both EX and EY, so even if with the filter disabled for EX, handing off to EY would break the lock.

New filter with correct sign was made, saved and loaded to the frontend: zpk([3225, [], -1, "n") in Hz/norm = zpk([-20263.27], [-32768], 1.617) in s.

Images attached to this comment
H1 General
nutsinee.kijbunchoo@LIGO.ORG - posted 20:41, Tuesday 09 February 2016 (25479)
OPS Eve Shift Summary

All time in UTC

1:20 6.3M earthquake in Chile prevented us from relocking

1:57 Robert to EY working on seismometers.

2:17 Robert done

2:22 Begins initial alignment

 

So far Jenne and I have been having trouble with locking ALS. Lockloss everytime the ifo tries to lock ALS DIFF (ALS COMM seems fine). We also coulnd't open the LSC DARM filter modules (DARM1 and DARM2). The files seems to have been removed (Jenne is about to recreate them). Seismic has come down to its nominal. Useism is hanging out near 50th percentile. Wind below 5mph. We know it's not environment issue.

H1 ISC
evan.hall@LIGO.ORG - posted 18:57, Tuesday 09 February 2016 (25476)
Intensity-to-DARM coupling TF

Related: 20148

I remeasured the intensity-to-DARM coupling by injecting into the ISS inner loop error point. The outer loop was not engaged.

The coupling is 0.2 mA/RIN at 100 Hz, or (after accounting for the loop and the optical gain) 4×10−14 m/RIN. This is consistent with Kiwamu's previous measurement.

Images attached to this report
H1 ISC
kiwamu.izumi@LIGO.ORG - posted 18:50, Tuesday 09 February 2016 (25477)
AS rack screen updated

Related to alog 25449. I have updated the ISC rack screen as shown in the attached.

Images attached to this report
H1 ISC
sheila.dwyer@LIGO.ORG - posted 18:29, Tuesday 09 February 2016 (25475)
AS45Q low frequency noise

The message:

Even if the excess low frequency noise on AS45Q when we are locked on DC readout is due to real DARM offset fluctuations, these are not large enough to cause any significant noise in band.

More details:

One of the ideas which has been suggested is that there may be some kind of lock point error in our DARM loop, which is modulating the DARM offset and causing noise through upconversion.  We see some excess noise in AS45Q compared to the DCPDs at frequencies below 1Hz, this could be a because of some lock point errors on either AS45 or the DCPDs.  

The first attached plot shows the two signals with and without a DARM boost and resonant gain that Evan tried out a few weeks ago.  You can see that boosting the DARM loop reduced both signals at frequencies where they agree, from about 7-2 Hz.  At lower frequencies boosting the DARM loop reduced the DCPD spectrum, but has no impact on AS45, the out of loop sensor.  From this we can say that one of the sensors has some kind of lock point error at these frquencies, but we don't know which it is.  

If we assume that the AS45Q sees the true DARM motion and the DCPDs have lock point errors, this could cause upconversion in DARM by modulating the DARM offset.  One idea would be to blend the two sensors, but we can also get an idea if this comes close to the DARM noise anywhere by looking at our data.  

I low passed the AS45 data at 5Hz, and added it to the DCPD residual to get an estimate of what the DARM fluctuations are if the AS45 noise is real (blue and green lines in second attachment). Then I repeated the estimate up upconversion due to DC readout from 25053

The projected noise (pink curve) doesn't come close to DARM except at a narrow line at the calibration line.  So it seems like we wouldn't expect to learn much by blending AS45 and DCPDs for DARM control.  

Images attached to this report
Non-image files attached to this report
H1 CDS (DAQ)
david.barker@LIGO.ORG - posted 17:55, Tuesday 09 February 2016 (25474)
CDS maintenance summary

Upgrade end station SUS front end computers with faster models [WP5728]

Robert, Carlos, Hugh, Dave, Jim:

The front end computers h1susex and h1susey were upgraded to the faster models. A brand new IRIG-B card which was installed in h1susey did not function correctly, and the card from the old computer was used instead. At both end stations the swap caused the other machines on the Dolphin fabric to hang, and therefore all models on h1seie[x,y] and h1isce[x,y] were restarted. The IRIG-B time on h1iopsusey dipped below zero for a short time (giving bad DAQ data and IPC receive errors). On h1iopsusex there was no IRIG-B time slew.

Hugh investigated the ISI payload watchdog as we tried to get SEI to ride through the SUS outage. We found several interesting things about this watchdog, and the main message was that it is not possible to bypass this watchdog before the sus mode is stopped. Turns out this was moot anyhow, since when the sus computer was powered back up the Dolphin fabric was disrupted.

All models were set back to OBSERVE sdf reference. The PEM ADC spare channels which were activated yesterday for Robert went back to their inactive SAFE state, using OBSESRVE state and REVERT I re-activated these.

With the faster computer and the original 2.6 kernel comes the periodic timing and adc errors on the sus machines. Since these errors usually latch on until a DIAG_RESET is issued, I am running a script on opsws16 which presses the DIAG_RESET button every minute on h1iopsuse[x,y] and h1susetm[x,y]. This will permit trending of these errors.

New PSL ISS model

Dave, Kiwamu:

Kiwamu installed his latest h1psliss model, this required a DAQ restart

New Beckhoff corner station PLC2 code

Daniel, Dave, Patrick:

Patrick installed new h1ecatc1plc2 code. I updated the DAQ INI and autoburt.req files. This required a DAQ restart

DAQ restart

Jim, Dave:

We restarted the DAQ once today for the above changes. The restart was clean. One interesting note is that h1fw0 started sufficiently before h1fw1 that it wrote our a full frame before h1fw1 got going.

Conlog

Dave, Jim, Patrick

After the autoburt .req file was regenerated, Patrick rescan the conlog channels. On restart he found that LAB DUST channels were missing. Jim tracked it down to a crashed IOC and restarted it.

SVN code cleanup

Dave:

I ran my ''check_h1_files_svn_status'' and committed all outstanding modifications. This resulted in updates for: front end mdl file (h1psliss), many filter files, many SAFE SDF snap files, many OBSERVE SDF snap files, many Guardian python scripts.

Partial filter loads full loaded

Dave:

I performed a full filter load on the two models which were running with possible partial loads: h1psliss, h1susitmy

H1 PSL
kiwamu.izumi@LIGO.ORG - posted 17:37, Tuesday 09 February 2016 (25473)
ISS model update

Under WP #5710

I applied another modification on the PSL ISS front end model as planned in alog 25316.

I tested the automatic engagement and adjusted the parameters so that it locks smoothly. The IMC_LOCK guardian code is updated to incorporate this new automation and has been tested multiple times.

I have not tested the engagement as part of the full locking sequence.


[The change in the h1psliss model]

As shown in the above attached screenshot, I added two functions last time (see alog 25316). Today, I have refined the automatic reference adjuster a bit by placing signal conditioning filters and etc. The above screenshot shows the final configuration I have implemented.

The concept is that when the second loop is open we set the reference coarsely using the manual slider (i.e. REF_SIGNAL_ANA). Then a fine tuning is done by feeding SECONDLOOP_SIGNAL (shown as a green tag) to the reference point. This will let the second loop operating point close enough to close the loop. Once the loop is closed, one can then optimize the diffraction power at the AOM by feeding the diffracted power back to the reference of the second loop. This choice can be done by a mtrix.

 

[The screen]

The latest screen now looks like this.

Images attached to this report
LHO VE (VE)
gerardo.moreno@LIGO.ORG - posted 16:46, Tuesday 09 February 2016 (25472)
Y-End Neg Regeneration

Regenerated NEG pump with the aid of an aux cart.
Valved out NEG from Y-End, then started regeneration of NEG pump ~18:30 utc.
2 hours later heating was complete, waited for temperature to drop down, valved in NEG pump to Y-End volume at 23:48 utc @ 34 deg C.
 

H1 SUS
keita.kawabe@LIGO.ORG - posted 16:33, Tuesday 09 February 2016 (25471)
H1SUSAUXEX and H1SUSAUXEY

Dewhitening filters for LVESDAMON were made and coefficients were loaded to H1SUSAUXEX and H1SUSAUXEY.

For the moment it's a simple zpk([40;40;965;965],[2;2],1,"n").

LHO VE
kyle.ryan@LIGO.ORG - posted 16:25, Tuesday 09 February 2016 (25470)
X2-8 BT ion pump HV cable short update
Today I attempted to find the short in the HV cable for the X2-8 BT ion pump (before proceeding with cutting off the extra cable length-unrelated task) as follows: 

I cut off the connector at the controller end and left the pump end connected to the pump.  I then connected the "Megger" (5000VDC @ 12mA) to the controller end of the cable and demonstrated that the short was still present.  I visually inspected the 100'+ excess cable for any obvious nicks or cuts (I did note one feature that looked like a clean incision or sharp slice).  I disconnected the pump end connector from the pump and let it hang in space -> No change.  Cable still shorted.  Finally, I cut-off the connector at the pump end and separated the conductors -> No change.  Cable short still present.  

Tomorrow I'll double check/inspect the run of cable that is in the HV raceway in the VEA and then proceed with cutting of the 100' extra cable length which will eliminate the incision "feature" previously noted and which I was going to do anyway prior to the appearance of the short.
H1 SUS
filiberto.clara@LIGO.ORG - posted 16:18, Tuesday 09 February 2016 - last comment - 05:08, Wednesday 10 February 2016(25468)
ETM ESD Electronics
Modified the ETM LVLN ESD Drivers (ECR E1500341):

1. Changed C32 in the monitoring amplifier from 1uF to 10nF to put the pole frequency at 4.244kHz
2. Changed C36 in the summing node from 1uF to 0.047uF to increase the dynamic range

EY Unit SN S1500066
EX Unit SN S1500073

Replaced the ESD AI chassis in SUS-C1 (EX/EY). New AI Chassis contains the PI Band Pass Filter D1500177. Cable H1:SUS_ESD-05 had to be re-terminated with a DB9 male connector to accommodate new AI front panel interface.
 
EY Old D1100815 Unit SN S1103824
EY New D1500177 Unit SN S1500300

EX Old D1100815 Unit SN S1103820
EX New D1500177 Unit SN S1500299
Comments related to this report
keita.kawabe@LIGO.ORG - 19:12, Tuesday 09 February 2016 (25478)

Evan, Keita

The above means that the actuation function changed due to C36 change.

That capacitor, together with R50 and R51, used to provide zpk([152], [3250]), but now this should be zpk([3225], [67725]).

Correction: used to provide zpk([3250], [152]), but now this should be zpk([67725], [3225]).

New digital compensation filter was made and the coefficients loaded to SUSETMX and SUSETMY.

Old compensation filter in L3 ESDOUTF antiAcq: zpk([152], [3250], 1, "n").

New one: zpk([3225], [], 1, "n"). The 67kHz pole zero in analog is ignored.

Attached is the transfer function from L3 ESDOUTF_LL_IN1 etc. to the LVESDAMON_LL_OUT_DQ etc.

LVESDAMON channels are with correct-ish dewhites mentioned in  alog 25471, so they are supposed to be transparent for f<1kHz.

If the new antiAcq filters in the actuation are good, the measured transfer function should be flat, and indeed all TFs measured look flat for 1<1kHz.

Images attached to this comment
daniel.sigg@LIGO.ORG - 05:08, Wednesday 10 February 2016 (25481)

The analog and digital filters seem to be the same? I guess the analog TF changed from zpk([3250], [152]) to zpk([67725], [3225]).

H1 General (VE)
hugh.radkins@LIGO.ORG - posted 16:09, Tuesday 09 February 2016 (25467)
CP3 CRYOPUMP Alarm removed from Alarm Handler

This should give a non-red state now for the VE unless something else is problematic so please respond to vacuum alarms.

H1 SUS
thomas.shaffer@LIGO.ORG - posted 16:06, Tuesday 09 February 2016 - last comment - 16:26, Tuesday 09 February 2016(25466)
Charge Measurements

The charge measurements for ETMX went well, but not great for ETMY. The measurement will loop through 5 times and we had almost finished the 2nd time when the SEI WD tripped and forced me to exit the running script, but I am not sure how good the data will be before the trip anyway. There wasn't enough time to run them again, so I tried to put back all of the settings differences, but I'm not 100% I did that correctly. I took screenshots, trended channels, and tried to mirror restored settings seen from the ending of the ETMX script. Hopefully it is all back where it should be.

I will post the plots in a few minutes from another computer.

Comments related to this report
thomas.shaffer@LIGO.ORG - 16:26, Tuesday 09 February 2016 (25469)

ETMX seems to be pretty consistent with the past plots, but ETMY can be a bit off. This isn't surprising since we bailed in the beginning of the ETMY measurement.

Definitely looks like it's time for a sign flip at both ends though.

Images attached to this comment
LHO General
corey.gray@LIGO.ORG - posted 15:58, Tuesday 09 February 2016 (25453)
Maintenance DAY Ops Summary

(All Times UTC)

Turned out to be a fairly long Maintenance Day, but hope to be locking soon.  Maintenance Activities ended just before 0:00UTC (4pmPST).

We decided to forego the ETMy Charge measurement this week, and Nutsinee will proceed with locking H1.

H1 SUS (CDS)
james.batch@LIGO.ORG - posted 15:49, Tuesday 09 February 2016 (25465)
Install new "fast" computers for h1susex, h1susey
WP 5728, Dave, Jim, Carlos

Install newer "Fast" computers for h1susex, h1susey.  These are the computers which were briefly installed in July of 2015 and were removed because they caused timing, ADC, and IPC errors.

The BIOS parameters for the computers are set to the optimal default with the exception of hyperthreading is turned off, the computers are set to stay off on power loss, the CPU power profile is set to maximum performance, and the boot order is changed to only look for DVD or PXE boot.  Initially, a much more restrictive set of parameters was tried, which disabled nearly all of the features settable from the BIOS, but it was found the models wouldn't run.

We have done nothing to correct the timing, ADC, and IPC errors which were observed in July.  We are monitoring the error rate so we have a good baseline for possible fixes in the future.
H1 CDS
patrick.thomas@LIGO.ORG - posted 14:37, Tuesday 09 February 2016 (25464)
Updated Conlog channel list
Updated channel list for h1conlog1-master. Channel changes attached.
Non-image files attached to this report
H1 CDS (CDS)
jonathan.hanks@LIGO.ORG - posted 11:09, Tuesday 09 February 2016 (25462)
Updated the slow controls SDF monitor code

The slow controls SDF IOCs have been updated to a newer release.  It is running RCG from trunk at revision 4114.

The SDF IOCs are configured to load straight to the OBSERVE.snap file (skipping the safe.snap which we do not use).

Changes:

With the precision changes I have accepted all numeric differences smaller than 10^-16.   These should not need to be accepted again until there is an actual change.

H1 CDS
patrick.thomas@LIGO.ORG - posted 10:33, Tuesday 09 February 2016 - last comment - 11:21, Tuesday 09 February 2016(25459)
Added IscRfCAsAmp90m channels to h1ecatc1
WP 5727

Yesterday Daniel and I changed h1ecatc1 PLC2 to replace IscRfCSpareAmp[1] of IscRfCSpareAmp[1..5] with IscRfCAsAmp90m. This morning I rescanned PLC2 in the system manager and added the links for IscRfCAsAmp90mIn and the lost links for the remaining IscRfCSpareAmpIn (now IscRfCSpareAmpIn[1..4]).

IscRfCAsAmp90mIn.OutputMon linked to Corner Chassis 6 L1 Channel 4
IscRfCAsAmp90mIn.PowerOk linked to Corner Chassis 6 L3 Channel 4

IscRfCSpareAmpIn[1..4].OutputMon linked to Corner Chassis 6 L2 Channel 1..4
IscRfCSpareAmpIn[1..4].PowerOk linked to Corner Chassis 6 L4 Channel 1..4

The wiring diagram also needs to be updated to show that IscRfCTcsAom40mIn.OutputMon is linked to Corner Chassis 6 L1 Channel 3 and IscRfCTcsAom40mIn.PowerOk is linked to Corner Chassis 6 L3 Channel 3.

Since everything was restarted I burtrestored PLC1, PLC2 and PLC3 to 6:10 this morning local time.
Comments related to this report
patrick.thomas@LIGO.ORG - 11:21, Tuesday 09 February 2016 (25463)
I updated the channel link list E1201049-v9.
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