I've turned all 4 RHs on to 2W total each (1W per segment) for 30 minutes this morning to get some data for Installation Acceptance. They will turn off again around 8:10AM.

The thermal lens should deteriorate to negligible by around 9AM, if not before.

Grills and dampers are installed in the DCS duct work. Remaining tasks include start up of the AC units, installation of the smoke detectors and some electrical.

Sheila, Dan, Daniel, Evan Jeff, Lisa, Alexa

Starting at 08:43:06 UTC Feb 11, 2015 we had a DC lock for ~1:54min. We lost lock again because of the 9 Hz bounce mode in ETMY. We had tried damping with the L2 stage, which helped a bit but still ultimately caused the lock loss.  Tomorrow we should try damping with M0, as done at LLO (LLO#16686).

We have seen in our two DC readout locks tonight what looks like it could be a fringe wrapping shelf in DARM. 

We transitioned to DC readout at 8:43:06 UTC Feb 11 and it is still locked.  If anyone could make a spectrogram of LSC-DARM_ERR durring this time, that would be interesting.  We made an attempt to do this using ldvweb, but didn't suceed yet.  

Alexa Daniel Dan Evan Jeff Lisa Sheila (+ many others)

Like a coffee hipster who won't touch beans that haven't passed through a civet, the IFO now measures DARM_ERR with the light transmitted through the OMC.

After the BS WFS were commissioned earlier today, we had several steady locks with 2.8W input power in which we attempted the handoff to DC.  We measured the DARM loop gain and set the UGF to be at the maximum of the phase bubble to make the transition as stable as possible (30Hz, ~30deg margin).  We experimented with different DARM offsets and settled on 5e-5 counts; with a preliminary calibration of 3x10^-7 m/ct this corresponds to an offset of 15pm.  The carrier TEM00 mode was somewhat larger than expected (see the attached pdf, peak at ~43 volts), about 15mA in DCPD sum, almost as much as the 45MHz sidebands.  We used this DARM offset for the rest of the evening.

We measured the OMC-DCPD_SUM --> DARM_IN1 transfer function and adjusted the OMC-READOUT_SCALE factor and LSC-OMC_DC_OFFSET to enable the handoff from AS45_Q.  The values we used are an offset of -2.33e-05 counts and a gain of -2e-6, these values were tuned at the few percent level in subsequent locking attempts to match gains as well as possible.  (Note that the gain comes before the offset, which makes trimming a little more straightforward.)  After these were applied the OMC-to-DARM noise TF looked like Fig. 1.  At this point we attempted the handoff to DC.

This blew the lock.  We realized the OMC input to DARM was subject to the normalization factor of sqrt(NPTRX).  We implemented an awkward fix by holding the output of the TR_X and correcting for the power normalization in the OMC-->DARM input matrix element.  The correction factor is 6.25, this changed by ~1% from lock to lock.

After that, the handoff to low noise worked.  The OMC DCPDs currently have no whitening enabled because the ETMY violin modes (at 508.1 and 508.2 Hz) are rung up and even a single stage of whitening will saturate the ADC.  So, we are ADC noise limited above ~400Hz.  One of our next steps will have to be the commissioning of the violin mode damping.  The ETMY bounce mode is also rung up; so far this isn't a problem, and we are nervous about turning on the damping before we're ready to end the lock.  A spectrum of the DCPD noise is in Fig. 2.