J. Kissel, T. Sadecki, D. Hoak, E. Merilh As a last ditch effort to be able to recocile the calibration for the rest of the run, given the drastic change to the ETMY ESD, I've completed a DARM OLGTF, and also tuned and completed a PCAL EX to DARM transfer function. I got halfway through the same transfer function using PCAL EY, but the lock broke from some sort of seismic disturbance. The interferometer was at 17 [W] requested input power for all of the below measurements, I attach the relevant digital parameters that are relevant (sadly the list is growing! as so many things are changing!). Analysis to come, but the measurements have been committed to the CalSVN repo here: /ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/PreER7/H1/Measurements/DARMOLGTFs 2015-06-13_H1_DARM_OLGTF_LHOaLOG19128_ETMYL3LPOFF.xml /ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/ER7/H1/Measurements/PCAL_TRENDS 2015-06-13_H1PCALEX_2_DARM.xml 2015-06-13_H1PCALEX_2_DARM_stronger.xml /ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/ER7/H1/Measurements/PCAL_TRENDS 2015-06-13_H1PCALEY_2_DARM_stronger.xml For the PCAL sweeps, I've modified the following settings from what Sudarshan had set up (2015-06-12_pcal_sweep_X.xml in the same folder) such that (a) the measurement would complete in a reasonable amount of time, (b) we'd get coherence over the entire band of measurement, and (c) that the frequency vector would match the DARM OLGTF: - Changed the frequency range to 5 to 5000 [kHz] - Changed the frequency vector from linear to logarithmic - Changed the user-defined amplitude format to Envelope - Increased the number of cycles to 25 - Increased the duration of a cycle to 1 [sec] - Increase the drive strength in various frequency bands where there remained no coherence
I took one more DARM OLG at 22.1 Watts, it is in the svn at /ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/PreER7/H1/Measurements/DARMOLGTFs/2015-06-14_H1_DARM_OLGTF_LHOaLOG191138_ETMYL3LPOFF.xml
LHO ER7 data quality shift Wednesday 6/3 to Friday 6/5 (1117378816-1117584015). TJ Massinger was the shift mentor.
Things we noticed:
- Thursday the sensemon was incorrectly generating the inspiral range, which has since been fixed. The range was between 45 and 55 Mpc on Thursday.
- The calibration accuracy seemed to be more widely varying than in previous days, with large departures (factor of >5) at the high frequency (~6kHz) end.
- We saw the 14Hz roll mode ringing down at the beginning of each lock, except for the 11:00-13:00 UTC segment Thursday, where a ring-down measurement was being performed. Nothing to see here.
- Some ugly wandering lines in CARM around 600Hz that also showed up through their 4th harmonic.
- A particularly glitchy segment just before 18:00 UTC Friday. We tracked down the loudest glitch which was identified as 2.16kHz (SNR 3,190). A time plot shows this was actually high frequency glitches riding on a much larger ~7.7 Hz blip. The high frequency components also showed up in the PRM M2 suspension control signals. Some discussion in the aLog about this: https://alog.ligo-wa.caltech.edu/aLOG/index.php?callRep=18918
A link to the shift report: https://wiki.ligo.org/DetChar/DataQuality/DQShiftLHO20150603
The calibratinon is wrong at the moment, I think the OMC's automatic scaling during the hand off failed. Dan confirms that he's changed the order o power scaling / gain matching yesterday. On the phone with sheila, I measure the DARM OLG, to be a factor of 0.63 too low, so with her advice, I've rescaled the sensing gain (in the LSC input matrix) by that same factor, 13.20723*1.5737 = 20.78447 then reconfirmed that both the DARM UGF is correct, as well as the DARM ASD on the wall matches the reference, and we're back in the reasonable Mpc range of ~55 [Mpc]. I'm now taking the full DARM OLGTF sweep, and if that's successful, I'll get the PCAL sweep as well.
Just to clarify - while the DARM OLG did change due to the OMC-READOUT_ERR_GAIN setting, this wasn't due to edits to the OMC_LOCK code. It's not clear why the gain-matching calculation missed on this lock, it worked fine for subsequent locks. Looks like a one-off error.
LLO was down at the beginning but came up during the injections. I did most of what I had hoped to do in the first round.
22:09UTC H1 is in science mode:
LLO showed up on DMT at ~ 20:48UTC
Robert into LVEA @ 20:47UTC
Jeff K into control room with a tour group @ 21:48
Still no locking for my shift. I talked to Sheila for a bit and it seems that when the ISC_LOCK guardian was getting stuck in LOCK_DRMI_1F asking you to adjust by hand, it was only in a PRMI configuration and SRM was misaligned somehow(perhaps related to what I was seeing during IA). I moved SRM around for a bit and brought it back to some old values but still nothing.
Ed will have to finish up the mess I made for him.
model restarts logged for Fri 12/Jun/2015
2015_06_12 23:27 h1fw1*
* = unexpected restart
I took over for Travis as the interferometer was locking DRMI, shortly after I had to damp ETMY and ITMX bounce and roll modes. It then made it to BOUNCE_VIOLIN_MODE_DAMPING before it broke. After recovery, it got stuck on LOCK_DRMI_1F for a long time, much longer than usual (25min is where I would give up) . I have heard this could be from a bad alignment so I did a quick initial alignment with no issues and then made it a few times to REFL_TRANS/RESONANCE before it broke lock.
Again LOCK_DRMI_1F took a long time so I did another initial alignment. This time, I struggled keeping the ALS locked. It would all seem good and then one of them would catch a flurry of large modes and then recover back to a steady power above 1. When I limped through IA to SRC_ALIGN, Guardian said that it was locked and it was not. This happens some times and is normally an easy fix but I couldn't make it work well at all, it was constantly moving around. I eventually got something that was round(ish) but pretty wavey and tried to move on. Made it to LOCK_DRMI_1F and it asked that I adjust it by hand, which is also not working.
That's the rundown of my shift so far, let's hope it improves.
Looks like an excitation got left on for H1SUSETMX. I saw it on the CDS Overview when I arrived, there are 6 test points running on it right now. I don't see anything in the alog about this being here intentionally.
Times UTC
5:13 Intent bit set to undisturbed. Note: calibration may have changed due to EY ESD issues.
5:18 Lockloss.
6:34 Intent bit set to undisturbed.
6:49 Lockloss.
Winds have calmed down since the beginning of the shift. Now a breezy 10-20 MPH.
Richard, Evan
It appears that the EY ESD bias was stuck at −430 V ever since the installation of the low-voltage driver in May. It became unstuck on 11 June, when Richard reset the driver.
Since we have always requested a positive bias for EY in the digital system (using SUS-ETMY_L3_LOCK_BIAS), this means that the reset on 11 June flipped the sign of the EY ESD actuation, causing the transition of DARM from EX to EY to fail (as TJ found).
To fix the transition, the EY bias is now requested to be negative in the digital system, thereby restoring the sign (but not the magnitude) of the true analog bias that we have had since 22 May. Of course, if the magnitude of the L3 actuation has changed, this will affect the accuracy of the calibration in the region dominated by the control signal.
First, let us enumerate some of the mysteries surrounding the EY ESD:
We hypothesize that mysteries (1), (3), and (4) are explained by the EY ESD bias being stuck at −430 V between 2015-05-22 and 2015-06-11, and the driver's readbacks being nonresponsive. Mystery 2 is still unsolved.
When Richard went to EY on the 11th, he found the high-range driver putting out −430 V on all five lines, and the driver's analog readbacks were frozen at −15000 ct or so. According to him, this is a known failure mode of the driver's microcontroller. After he reset the driver, the analog readbacks became functional again.
The attached plot shows a trend of the analog readback of the EY ESD bias. It is stuck at about −15000 ct from 2015-05-22 (when the low-voltage driver installation was finished) to 2016-06-11 21:00:00ish UTC (when Richard reset the driver). The natural conclusion from this is that the EY ESD bias has been railed at −430 V between these two dates (even though we thought we were giving +380 V of bias).
I flipped the requested bias so that it is now (I think) −380 V, which is the most negative bias that can be requested from the driver when it is operating properly. I was able to transition control of DARM from EX to EY by hand following the steps in the guardian.
Also, Travis and I are hearing ETMY saturations every so often. The rms drive to EY L2 is 40000 ct or so, which is higher than the 15000 ct that we measured when we first started using EY L2. (Could it just be wind?)
If you, like us, don't like it when your suspensions saturate in full lock, then we suggest trying out a higher L1/L2 crossover. Engage FM9 in H1:SUS-ETMY_L1_LOCK_L, and turn up the gain from 0.16 to 0.31.
Per Jeff's request, here is an excerpt from an email I sent to Evan and Jeff: Some architectures used in amplifiers suffer from a phenomenon known as Phase Reversal wherein the feedback sign of the amplifier can actually change on certain saturation events. I have not looked to see if that is whatsoever possible with the HV ESD amplifiers. Something that bothers me here is that if you are running in low voltage mode, there is no way the high voltage drive signals for the quadrants can make it to the reaction mass. A relay disconnects them. This makes me somewhat puzzled about potential HV/LV interactions causing any sort of actuation force reduction. The actual applied bias could be changing by the time it makes it through the non-trivial series resistance associated with the bias filters (~70kohms), but there would have to be a low impedance on the bias terminal to created the necessary voltage divider. As for the sign flip, I have no answer there. I will check (again) that I didn't do something dumb and make a typo on the + and - wires.
Following up on the notion of phase reversal, I checked all the chips used in the HV ESD Driver signal chain. Here's the result: LT1124 - Input receiver, these are the same architecture as the ubiquitous LT1125 we use everywhere at LIGO, so I'm not too suspicious here. LT1007 - Second stage of input receiver, no mention of immunity to phase reversal in data sheet. This is often a bragging point among chip designers, so I can't eliminate this chip from the list of suspects. OP-97 - Front end chip for the HV output stage, Vcm = +/-13.5V min, this is a possible culprit as the input architecture appears to be jfet based, and it's used in a feedback loop, which is a double whammy for phase reversal. PA-95 - HV driver chip. No mention of phase reversal immunity. Definitely jfet based, used in a feedback loop, and is not grounded on the positive pin. Triple whammy for phase reversal, although it would be hard to exceed the input common mode voltage with +/-430V rails... Mostly pseudo science here, but my two cents.
No luck locking so far. Winds are an issue once again, 20+ MPH with gusts over 40 MPH. Commissioners may have discovered an issue with the EY ESD which could have been partially to blame for the lack of locks in the past day. Talked to Gary in the LLO CR again and let him know we are in for another tough night.
We had four known reasons for having difficulty locking today, one is an unsolved mystery that might be hurting us more often than we realize.
I reloaded both ISC_DRMI and ISC_LOCK guardians today, to incorporate these changes.
Good luck TJ!
I don't think the log snippet included above shows the problem, but I found where in the log it does:
2015-06-13T05:36:35.76316 ISC_LOCK [LOWNOISE_ESD_ETMY.enter]
2015-06-13T05:36:35.78009 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_TRAMP => 0
2015-06-13T05:36:35.78025 ISC_LOCK [LOWNOISE_ESD_ETMY.main] Preparing ETMY for DARM actuation transition...
2015-06-13T05:36:36.03624 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_M0_LOCK_L => OFF: INPUT
2015-06-13T05:36:36.03791 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L_GAIN => 0.16
2015-06-13T05:36:36.03886 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_GAIN => 0
2015-06-13T05:36:36.04021 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L_SW1S => 20804
2015-06-13T05:36:36.29496 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L => ONLY ON: INPUT, FM2, FM3, FM5, FM6, FM7, FM8, OUTPUT, DECIMATION
2015-06-13T05:36:36.55096 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L2_LOCK_L => ONLY ON: INPUT, FM6, OUTPUT, DECIMATION
2015-06-13T05:36:36.55229 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_SW1S => 16388
2015-06-13T05:36:36.80324 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L => ONLY ON: INPUT, FM6, FM8, FM9, FM10, OUTPUT, DECIMATION
2015-06-13T05:36:37.05938 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L2_DRIVEALIGN_L2L => ONLY ON: INPUT, FM2, OUTPUT, DECIMATION
2015-06-13T05:36:37.31538 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_DRIVEALIGN_L2L => ONLY ON: INPUT, FM3, FM4, FM5, OUTPUT, DECIMATION
2015-06-13T05:36:37.31694 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_TRAMP => 10
2015-06-13T05:36:37.32341 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMX_L1_LOCK_L_SW1 => 16
2015-06-13T05:36:37.57613 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMX_L1_LOCK_L => OFF: FM1
2015-06-13T05:36:38.57792 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_GAIN => 0.7
2015-06-13T05:36:38.57846 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMX_L3_LOCK_L_GAIN => 0.5
2015-06-13T05:36:49.58941 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L_SW1 => 16
2015-06-13T05:36:49.84053 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L => ON: FM1
2015-06-13T05:36:50.84245 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_GAIN => 1.25
2015-06-13T05:36:50.84585 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMX_L3_LOCK_L_GAIN => 0
2015-06-13T05:36:50.84640 ISC_LOCK [LOWNOISE_ESD_ETMY.main] timer['ETMswap'] = 10.0
2015-06-13T05:36:50.85290 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_TRAMP => 0
2015-06-13T05:36:50.85341 ISC_LOCK [LOWNOISE_ESD_ETMY.main] Preparing ETMY for DARM actuation transition...
2015-06-13T05:36:51.10580 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_M0_LOCK_L => OFF: INPUT
2015-06-13T05:36:51.11470 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_GAIN => 0
2015-06-13T05:36:51.11670 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L_SW1S => 20804
2015-06-13T05:36:51.37015 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L => ONLY ON: INPUT, FM2, FM3, FM5, FM6, FM7, FM8, OUTPUT, DECIMATION
2015-06-13T05:36:51.62486 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L2_LOCK_L => ONLY ON: INPUT, FM6, OUTPUT, DECIMATION
2015-06-13T05:36:51.88017 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L => ONLY ON: INPUT, FM6, FM8, FM9, FM10, OUTPUT, DECIMATION
2015-06-13T05:36:52.13170 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L2_DRIVEALIGN_L2L => ONLY ON: INPUT, FM2, OUTPUT, DECIMATION
2015-06-13T05:36:52.38753 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_DRIVEALIGN_L2L => ONLY ON: INPUT, FM3, FM4, FM5, OUTPUT, DECIMATION
2015-06-13T05:36:52.39457 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_TRAMP => 10
2015-06-13T05:36:52.65332 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMX_L1_LOCK_L => OFF: FM1
2015-06-13T05:36:53.65498 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_GAIN => 0.7
2015-06-13T05:36:53.65562 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMX_L3_LOCK_L_GAIN => 0.5
2015-06-13T05:37:04.66682 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L_SW1 => 16
2015-06-13T05:37:04.91783 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L1_LOCK_L => ON: FM1
2015-06-13T05:37:05.91955 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMY_L3_LOCK_L_GAIN => 1.25
2015-06-13T05:37:05.92183 ISC_LOCK [LOWNOISE_ESD_ETMY.main] ezca: H1:SUS-ETMX_L3_LOCK_L_GAIN => 0
2015-06-13T05:37:05.92216 ISC_LOCK [LOWNOISE_ESD_ETMY.main] timer['ETMswap'] = 10.0
2015-06-13T05:37:05.94222 ISC_LOCK [LOWNOISE_ESD_ETMY.run] MC not locked
Based on the ezca and log output during LOWNOISE_ESD_ETMY.main it
does in fact look like main() was executed twice in a row. That should never happen under any circumstances. I'm investigating.
I think that there are potentially two different issues, one being what is shown in the original alog, where the run should return true, but the guardian state doesn't change even though the current state is not the requested state. We could re-wrtie the guardains (or at tleast this state) to reduce the harm from this, but it still seems like a bug in the way the gaurdian is working.
On the other hand, the problem that Jamie pointed out is more serious. For other reasons, I have been looking at histograms of how long the guardian spends in each state. Some states should take the same amount of time to execute each time, but analog carm for example has 3 possibilities. We often detect a lockloss in the first second of the state, if the state executes normally it takes 18 seconds, but there were 5 times that it took 35 seconds because it repeated main. GPS times of these events are:
1117983542.06250
> 1118037936.06250
> 1118148903.93750
> 1118294947.06250
> 1118295997.06250
I looked at guardian log for the first three of these events, and indeed they
are times when the main was repeated. These are mosly sucsesfull locks, so the bug isn't causing locklosses here although it easily could.
The ISC_LOCK code that was running at the time is in the svn as revision 10776.