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Reports until 16:07, Tuesday 26 May 2015
H1 SUS
betsy.weaver@LIGO.ORG - posted 16:07, Tuesday 26 May 2015 (18633)
ETMy SDF diffs over the weekend - ETMy may or may not be in configuration

Just a heads up to commissioners:

I took a snapshot of the ETMy SDF diffs that popped up over the weekend of commissioning this morning.  After Kissel's model fix from this morning, the diff list is smaller now.  This may imply that some of the purposeful changes made to ETMy over the weekend have been undone -  it is hard to tell because many of the things that were on the larger diff list from before the reboot were people likely "just testing" things that weren't working over the weekend.  Or, there are some settings guardian is switching since we're not back up and lots of testing is taking place right now (meaning, I haven't caught them all and made SDF ignore them yet).  Or, the reboot and sweep through the GRD SAFE-DAMp settings cleared house.

In any case, I post the before and after list in the event ETMy still is not acting properly for the evening commissioners and they are looking for "previous" settings..

Images attached to this report
LHO VE
kyle.ryan@LIGO.ORG - posted 15:33, Tuesday 26 May 2015 (18632)
Added shims to CP2 LLCV to gaurantee minimal flow through transfer line while PID loop adjusts to today's overfill
Praxair delivery today resulted in CP2 overfill -> PID loop will eventually shut-off LN2 flow through transfer line as a response -> Warm transfer line will likely result in secondary under fill alarms tonight -> shimming LLCV slightly open will keep transfer line cold regardless of PID output to LLCV 
H1 SEI
thomas.shaffer@LIGO.ORG - posted 14:54, Tuesday 26 May 2015 (18629)
BRS Restart

Jim W., TJ

SYS_DIAG reported that BRS had flatlined, and after looking into it it looked like the software crashed on Saturday (attached image). The BRS is not currently being used for sensor correction so this was not a big deal but we did need to restart it. I took a trip down to EX, followed the instructions on Alog 13817, drove back and realized that that had not corrected the problem. I took Jim with me this time and he noticed that the rate box on the running analysis screen was empty. He restarted it again and it all seemed to work well. Everything looks good now.

Images attached to this report
H1 CAL (CDS, DetChar, ISC, SUS)
jeffrey.kissel@LIGO.ORG - posted 14:30, Tuesday 26 May 2015 (18628)
Precision Transfer Functions of H1 SUS ETMY AI Chassis
J. Kissel

Another belated aLOG: I've measured the ETMY AI chassis this past Wednesday morning in an identical fashion as to how I'd measured ETMX in 18518. See attached set of plots, but more importantly fo use later, the data lives in 
/ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/PreER7/H1/Measurements/ElectronicsMeasurements/H1SUSETMY_L1_*.txt
which has been processed by 
/ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/PreER7/H1/Measurements/ElectronicsMeasurements/process_H1SUSETMY_AI_Measurements_20150520.m

As with ETMX, all relevant AI chassis channels on M0, L1, L2, and L3
- are fully functional,
- have a "DC" gain of 0.9902 +/- 0.0001 [V/V] gain (measured at 10 [Hz])
- have a notch frequency of 65838 +/- 277 [Hz]
- drop to 0.976 [V/V] in magnitude and lose 27 [deg] in phase (again no surprise).
These measurements will be used to inform the calibration model, as opposed to what we're currently using which had been the mean and std of several hundrend generic AI/AA filter boards that had been tested (and done so prior to the -v6 upgrade). That being said, there's very little difference between the two, so there will be little to no change.


Non-image files attached to this report
H1 SUS (CDS, DetChar, ISC)
jeffrey.kissel@LIGO.ORG - posted 14:11, Tuesday 26 May 2015 (18622)
Binary IO Fixed for H1SUSETMY's new Low-Noise ESD , and now independent fron TMSY; Tidal Path Bug Fixed
J. Kissel, D. Barker, J. Batch, R. McCarthy, R. Abbott

First: Thanks to all that aLOGged / documented what we had installed / debugged for the new low-noise ESD driver in my absence, (i.e. LHO aLOGs 18559, 18592, 18568). Apologies for not having time for the true systems level check-out and not committing my work!

Second: The messages -- 
(a) The new BIO control and monitoring for the low-voltage ESD driver at H1SUSETMY is now independent of the H1SUSTMSY's BIO. To do so, we had to move the Binary Input and Output cables two ports "up" from channels 16-23 & 24-31 (as originally designed in D1400177-v4) to channels 32-39 & 40-47, and change the front-end code mapping in the h1susetmy.mdl model accordingly.
(b) I've fixed the bug which mapped the IPC error rate signal for the Tidal Correction into the main "library" block. It's now feeding the actual signal to the main library block as one might expect.

Details
--------
I've installed new infrastructure to support the BIO monitoring and control of switches inside the new low-noise ESD driver. Mostly* following the drawing shown in D1400177-v4, the driver has five groups of functions that are controlled and monitored: (follow along with the block diagram D1400301)
(1) HI VOLT DISCONNECT: there are four (one for each ESD quadrant) independently switchable relays on the input (marked as S1, S2, S3, and S4) that either engage the High Voltage ESD driver, or ground that connection and only use the Low Voltage Driver
(2) Low-pass filter switching (STATE REQUEST on the BIO MEDM screen): again four (on for each ESD quadrant) independently switchable relays to engage a z:p:k = [ 50,50 : 2.2,2.2 : 1 ] low pass filter (for more accurate description of poles and zeros, see the now-measured transfer function LHO aLOG 18579). 
     State 1 : Low Pass OFF
     State 2 : Low Pass ON
     [Bonus states, as with any coil driver: State 0: ISC control (currently terminated); State -1 or -2: same as above but use has control over digital compensation filters]
(3) HI/LO VOLTAGE: four, independently switchable relays  toward the output of the driver that select using the output of the High Voltage driver or bypassing it entirely (if the HI VOLT DISCONNECT is switched to DISCONNECTED). 
(4) RIGHT / LEFT PI SWITCH: For the not-yet commissioned parametric instability path (whose control signal will eventually come from an independent front-end model running at 64 [kHz]) one can independently chose whether to drive the upper or lower quadrant of the LEFT and RIGHT sides.
(5) HV ESD DRIVER TRIP RESET: This functionality should match the functionality of the red button on the front of the High Voltage driver -- when the driver trips, this is its momentary RESET button.

All of these switches are controlled via Binary I/O in the h1susetmy. They're packed up into a 16-bit word that gets fed to the binary IO card (see the generation of this word in 
2015-05-26_H1SUSETMY_BIO_L3.png). Note that for the low-pass filter switching (STATE REQUEST on the BIO MEDM screen) I've created a new sub-function to
/opt/rtcds/userapps/release/sus/common/src/CD_STATE_MACHINE.c
which is basically identical to the TOP driver's function, but without a test-coil enable, because it's a similar two-state machine (a state machine diagram will be added to T1100507 in the fullness of time).

Problem (a) was a result of piping this 16-bit control word into the "upper" half (bits 16-31) of the "lower" 32 bits (bits 0-31) of the 2nd (Card "1") of the h1susey 64-bit binary I/O cards, which is what the TMSY was already using to control its TOP mass coil driver switching (who was using the "lower" half, bits 0-15 of that same "lower" 32 bits of the 2nd card). Recall that the RCG must artificially split the 64-bits into two 32-bit words (the "lower" (0-31) and "upper" 32 (32-63), referred to as L32 and H32, respectively). However, it turns out that two front-end models cannot share one of these upper or lower halves, even though in analog land one might suspect that one might even be able to break the card up into even 8-bit word chunks. Thankfully the BI and BO chassis have virtually all of their spigots free, so we just shifted the cables "up" so that they came in on the "upper," H32 "card" and modified the front-end code accordingly to match (see 
2015-05-26_H1SUSETMY_SimulinkModel.png, and please forgive the mislabeled BIO ENCODE spigot that says it's still outputing the "L32" bits. This is an inconsequential remnant of the bug fix that I only noticed while writing this log, and I don't want to 4-R the front-end code just for a label fix.)

Problem (b) was just a byproduct of my haste in getting these front-end changes done. While cleaning up the top level of the model, I just misconnected the new FLAG / TAG for the tidal servo signal to the IPC error rate. Sorry about that.

-------
The following has been committed to the userapps repo (recall the top level, main control system part of model is *already* unhooked from the library because of how tidal corrections have been implemented):
/opt/rtcds/userapps/release/sus/h1/models/h1susetmy.mdl  SORRY FOR NOT DOING THIS EARLIER!!
/opt/rtcds/userapps/release/sus/common/src/CD_STATE_MACHINE.c 

The following has be consciously NOT committed to the repo (because it will conflict with changes already made to support ECR E1500228):
/opt/rtcds/userapps/release/sus/common/medm/quad
SUS_CUST_QUAD_OVERVIEW.adl
SUS_CUST_QUAD_BIO.adl
 
Images attached to this report
H1 SUS
betsy.weaver@LIGO.ORG - posted 13:51, Tuesday 26 May 2015 (18617)
On-going cleanup of SDF

1)  Found that the ETMx misaligned offsets were changed at 9am on Monday morning.  H1:SUS-ETMX_M0_TEST_P_OFFSET went from -107 to -307 suspiciously.  The YAW offset only changed by 10e-3 which is negligable.

No alogs as to why, and Kiwamu agrees that they should be set back to what they were last week.  Since the decimal places went out to the 10e-8 place unnecessarly, I've rounded to 10e-1.

2)  I zeroed a bunch of large +/- 20000 offsets that were loaded (but not turned on) in the ETMY COILOUTF OFFSETS.  Also, un-alogged as to why they were there - likely testing left over from last week??

3)  Ignored new DAMP MODE TRAMP channels all ETM/ITMs.

4)  Accepted new weekend DAMP MODE filtering on ETM/ITMs.  These likely will keep popping up but now should be set to NOT MON since commissiones have written these into GRD over the weekend.

LHO VE
kyle.ryan@LIGO.ORG - posted 13:31, Tuesday 26 May 2015 (18627)
0900-1200 Short low temp bake of BSC6 RGA
Kyle 

Ran pump cart during this period
LHO VE
kyle.ryan@LIGO.ORG - posted 13:29, Tuesday 26 May 2015 (18626)
Made change to Y-mid ion pump controller
Kyle, Gerardo 

Pump 1 channel in "STEP" mode -> changed to 5000V "FIXED" -> Both mid station ion pumps fixed at 5000V (historically) -> May change both to 7000V fixed to be consistent with all other pumps (next maintenance day?)
H1 PSL
jason.oberling@LIGO.ORG - posted 12:23, Tuesday 26 May 2015 - last comment - 12:31, Tuesday 26 May 2015(18624)
PSL Maintenance

J. Oberling, P. King, E. Merilh

Summary

Today we went into the PSL enclosure to increase the front end (FE) diode currents and tweak the PMC and FSS alignment.  We:

  • Added ~2A of current to the 4 FE diodes and tweaked their operating temperature.  We now have 33.1 W out of the FE.
  • Tweaked the PMC alignment and now have a transmitted power of 22.9 W, a reflected power of 2.4 W, and a visibility of 89.9%.
    • We will have to go back in at a later date and adjust the PMC mode matching lenses, L02 and L03, to improve the PMC transmitted power; we ran out of time today.
  • Tweaked the FSS alignment to increase the RefCav transmission and now have a RefCav TPD reading of 1.47 V and a visibility of 72.3%.
  • Checked the DBB RPD voltage to make sure it was above 9 V so we could continue to make measurements with the DBB.  It is at 9.53 V.  We also measured the power into the DBB along the 35 W laser path as 150 mW; this is >135 mW, so all is good.

Details

FE Diodes:

We added ~2A to the 4 FE diodes to increase the FE power, which had been slowly drifting down over the last several months (threshold for diode current adjustment is 5% drop, we were at ~7%).  Both power supplies are now feeding ~51A to the FE diodes.  We then had to optimize the temperature of the diodes to maximize the FE power.  Peter took before/after screenshots of the FE diode settings and will post them as a comment to this log.  We are now reading 33.1 W out of the PSL FE.

PMC:

We then proceeded to tweak the PMC alignment.  We adjusted both pitch and yaw on mirrors M06 and M07 and were able to get 22.9 W of transmitted power, with 2.4 W of reflected power.  This is obviously not ideal (we want reflected power to be <10% of transmitted power), but all we could do within the alotted maintenance window.  We will have to go back in at a later date and adjust the 2 mode matching lenses, L02 and L03.

Looking at the PMC RPD, it has a locked reading of -0.154 V and an unlocked reading of -1.52 V, giving a PMC visibility of 89.9%.

FSS:

We tweaked the alignment of the RefCav input periscope in both pitch and yaw and improved the RefCav transmission (as read from the RefCav TPD) from 0.75 V to 1.4 V.  We then adjusted the AOM in pitch/yaw to see if we could improve the TPD reading further.  We were able to improve the TPD to ~1.47 V.

Looking at the FSS RefCav RPD, it has a locked reading of 0.072 V and an unlocked reading of 0.260 V, giving a RefCav visibility of 72.3%.

DBB:

We opened the DBB shutters along the 35W laser path to measure the voltage on the DBB RPD; this has to be between 9 V and 11 V for proper DBB operation.  We measured it at 9.53 V.  We also measured the power into the DBB along the 35W laser path at 150 mW; this is >135 mW, so all is good here.

Comments related to this report
peter.king@LIGO.ORG - 12:31, Tuesday 26 May 2015 (18625)
The initial diode currents for diodes 1/2 and 3/4 were 49.0A.  To bring the pump
light monitors back up to 100% the currents were increased to 51.3A and 51.0A
respectively.

The diode temperatures were changed too.
D1, was 18.0 degC, is now 17.0 degC
D2, was 20.0 degC, is now 17.5 degC
D3, was 20.0 degC, is now 19.0 degC
D4, was 20.0 degC, is now 19.0 degC
Images attached to this comment
H1 CDS
patrick.thomas@LIGO.ORG - posted 12:22, Tuesday 26 May 2015 (18623)
Updated Conlog channel list
Greened up for engineering run. 119 channels added. 10 channels removed. H1:SUS-SR2_LKIN_P_OSC_SW2R and H1:SUS-SR2_LKIN_Y_OSC_SW2R were manually added to the exclude list. No unmonitored channels remain.
H1 CDS
patrick.thomas@LIGO.ORG - posted 12:02, Tuesday 26 May 2015 (18621)
Took backup of h1conlog1-replica database
Copied compressed tarfile of logical database dump to /ligo/lho/data/conlog/h1/backups/h1conlog_dump_2015_05_26.sql.tgz. 5.8 GB.

Completes WP 5226.
H1 CDS
nutsinee.kijbunchoo@LIGO.ORG - posted 12:00, Tuesday 26 May 2015 (18620)
EX Beckhoff Restarted

Patrick, Nutsinee

... burtrestore to 05/26 06:10.

H1 CDS (SEI)
james.batch@LIGO.ORG - posted 11:35, Tuesday 26 May 2015 (18619)
Replaced power supply in h1seih45 I/O Chassis
Richard, Dave

After a failure over the weekend in which DAC and ADC cards could not be detected in the I/O chassis (alog 18603), we replaced the power supply.  The removed supply will be installed in the DAQ test stand for testing.
H1 CDS
betsy.weaver@LIGO.ORG - posted 11:13, Tuesday 26 May 2015 (18618)
tp clear of EXCs

This morning I noticed a few EXC flagged as enabled on the CDS overview.  After a roll around the room, Kissel and I cleared the LSC TPs on H1CALCS and H1SUSETMY.

H1 General
vernon.sandberg@LIGO.ORG - posted 09:34, Tuesday 26 May 2015 (18616)
Proposed Calendar for the ER7 Run

Engineering Run 7

Schedule

1 Start of Calibration for ER7 (starts after maintenance at LHO)   Tuesday, 2015 May 26 12:01 pm PDT, 2:01 pm CDT
2 End of Calibration for ER7   Friday, 2015 May 29 12:01 pm PDT
3 Start of "Annealing" for ER7   Friday, 2015 May 29 12:01 pm PDT
4 End of "Annealing" for ER7   Tuesday, 2015 June 2 7:59 am PDT
5 Maintenance (four hours every Tuesday 8:00 - Noon local time)   Tuesday, 2015 June 2 8:00 am - Noon
6 Buffer before start of ER7, to be used as needed   Tuesday, 2015 June 2 12:01 pm PDT - Wednesday, 2015 June 3 7:59 am PDT
7 Start of ER7   Wednesday, 2015 June 3 8:00 am PDT, 10:00 am CDT
8 Maintenance   Tuesday, 2015 June 9 8:00 am - Noon
9 End of ER7   Monday, 2015 June 15 7:59 am PDT, 9:59 am CDT
10 Start of Vent at LHO   Monday, 2015 June 15 8:00 am PDT, 10:00 am CDT

Daily Global ER7 Run Status and Planning meeting will take place daily at 1:00pm PDT / 2:00pm CDT / 3:00pm EDT on the JRPC "TeamSpeak" channel. The plan is for a short meeting that provides updates and plans for the two interferometers and the data analysis community. This meeting will start on Tuesday, May 26, 2015.

H1 ISC
evan.hall@LIGO.ORG - posted 06:33, Tuesday 26 May 2015 - last comment - 22:45, Wednesday 27 May 2015(18613)
Trying to power up

Dan, Kiwamu, Evan

Summary

Tonight we worked on getting the interferometer back to its low-noise state. We are stable at 10 W, but there is some instability at higher powers.

Details

ITM steering

First, at 3 W we manually steered the ITMs to a good recycling gain (38 W/W), and then updated the TMS QPD offsets. We also locked the arms in green, adjusted the green QPD offsets for maximum buildup, and then updated the ITM camera references. Then we re-enabled the ITM loops in the guardian. This allowed us to power up all the way to 21 W without significant degredation of the recycling gain.

After that, we were able to consistently engage the ASC with the guardian.

Power-up issues

However, we found that at 21 W the interferomter suddenly unlocks in a matter of minutes. There seems to be no instability in the arm or sideband buildups before the lockloss. We looked at OMC DCPD signals for signs of PI, but we did not see anything ringing up during any of our short high-power locks. Some times to look at are 02:29:50, 02:59:50, 04:57:30, 06:55:00, all 2015-05-26 UTC. But any of the other 21 W locklosses in the past 12 hours follow this pattern.

We measured the OLTFs of PRCL, MICH, SRCL, and DARM before and after powering up, but they all look fine and did not change with power. For CARM, we start at 3 W with a UGF of 14 kHz with 47° of phase. Then during power-up, the electronic gain is automatically adjusted to compensate for the increased optical gain. The algorithm for this was shooting a little high, so after power-up the UGF was more like 27 kHz with 30° of phase. This is probably fine, but we adjusted the algorithm anyway, so that the UGF is placed at 19 kHz, with 45° of phase. Anyway, this did not solve the lockloss issue.

We also tried locking at some lower powers. At 15 W the interferometer lasted for about 15 minutes before unlocking. At 10 W, the lock time seems to be indefinite (at least 90 minutes).

DARM crossover

Using FM9 in ETMY L1 LOCK L (zero at 2 Hz, pole at 5 Hz), we were able to push the L1 crossover from <1 Hz to 1.7 Hz by adjusting the filter gain from 0.16 to 0.31. Measurement attached, showing before and after. This is not included in the guardian. By pushing up the crossover, the rms drive to L2 decreases from >10000 ct to about 6000 ct or so.

Other

For the record, we did not notice any kicks to the yaw of IMC REFL tonight.

Non-image files attached to this report
Comments related to this report
daniel.hoak@LIGO.ORG - 08:02, Tuesday 26 May 2015 (18614)

New Damping Settings for Bounce, Roll, Violin modes

Over the weekend we were able to re-commission the damping of the bounce, roll and violin modes.  The bounce & violin damping settings have been propagated to the ISC_LOCK guardian, and should be stable (maybe).  The roll mode settings have already changed once over the weekend, so I'll list what's been working, but your mileage may vary.

The attached spectrum (for 10W, low-noise ESD, *not calibrated*, no LSC FF, so don't study it too closely) shows the mode-damping progress.  Note this was before the 2.4k and 2.8k violin harmonics were damped.

 

Bounce modes:

After struggling to apply very narrow band-pass filters a la Jeff's approach from alog:18483, we reverted to the method of very broad band-passes.  These are loaded as FM3 in the DARM_DAMP_V filter banks.  The frequencies follow those listed by Sheila in alog:18440 (we confirmed these frequencies were correct through the course of our damping exercise).

  ETMY ETMX ITMY ITMX
Frequency [Hz] 9.73 9.77 9.81 9.85
Filters FM1 (+60deg), FM3 FM3 FM1 (+60deg), FM3, FM6 (+30deg) FM2 (-60deg), FM3
Gain -0.3 -0.5 +1.0 +0.3

The real key to squashing the bounce mode peak was to work out the damping settings for ETMX and ITMY (the optics which couple bounce --> longitudinal motion the least).  The extra 30deg of phase for ITMY turned out to be important.

 

Roll modes:

We were able to damp the ITMX roll mode, thus breaking the unpaired set of frequencies for roll modes and assigning each peak to an optic.  The ITMX roll mode wasn't rung up this weekend, so we didn't have a chance to work out damping settings.  The sign for damping the ETMY roll mode flipped between Sunday and Monday night, otherwise these damping settings were pretty stable.

For all the TMs the FM4 filter is a broad band-pass from 13.5 to 14.5Hz.

  ETMY ETMX ITMY ITMX
Frequency [Hz] 13.816 13.889 13.930 13.978
Filters FM3 (-100dB), FM4, FM6 (+30deg) FM3 (-100dB), FM4 FM3 (-100dB), FM4 ??
Gain -20 +600 -80 ??

The roll mode is rung up after every lockloss (usually it's ETMY), so these settings need to be manually applied before the transition to DC readout.  The gains listed in the table above are the "high-gain" damping state, if the mode is very rung up you need to start at a lower gain setting or you might saturate the M0 stage.

 

Violin Modes

Recall that violin mode frequencies and their associated test masses were given in alogs 17365, 17502, and 17610.

All the identified modes are well-damped and have been enabled in the Guardian code, with the exception of ITMX.  Despite many attempts I haven't been able to actuate on the ITMX modes at all.  Before the realignment/recycling gain work the ITMX modes damped very easily, now I can't find a DOF (longitude, pitch, or yaw) or a phase setting to move the modes either up or down.  It's hard to believe the L2 stage of ITMX isn't working, so we're not sure what the problem is.  Maybe we just need more patience.

The complete set of violin mode damping settings is too large to list here; the various filters and gains are recorded in the guardian code.  Some modes require a specific filter to get the right phase, others can be grouped together with broad band-pass filters without much trouble.  In particular, ITMY requires separate filters for each mode, it's very difficult to construct a broad band-pass that catches more than one mode with the correct phase.  We need to add more filter banks to the L2 DAMP section of the quad models if we want to squash the violin modes and their harmonics.

We did identify some new modes -- since we started feeding DARM back to the ETMY L2 stage we rang up the 4th, 5th, and 6th harmonics of that optic.  These modes were easily damped and have been notched in the actuation path. The specific frequencies and damping settings were:

2424.38, 2427.25 Hz: Use FM6 of ETMY L2 DAMP MODE1, +60deg of phase, +100dB, gain=+20k, longitudinal direction

2878.7, 2882.5 Hz: Use FM6 of MODE2, no phase, gain=+10k, longitudinal direction

3330.6 Hz: Use FM5 of MODE3, -60deg of phase, gain=+20k, longitudinal direction

3335.7 Hz: Use FM6 of MODE3, no phase, gain=+20k, longitudinal direction

Images attached to this comment
sheila.dwyer@LIGO.ORG - 22:59, Tuesday 26 May 2015 (18630)

Keita, Sheila

In three of last night's 10 Watt locklosses, as well at the 15 Watt lockloss, the CARM loop dropped first, when IMC-F reached something around +/- 1440 kHz (the first screen shot attached is typical, 2015-05-26 15:23:17, 13:228:28, 12:10:29, and 7:38:16 at 15 Watts).  Now that Jeff has fixed the model and we are using tidal again, this type of lockloss has not been bothering us tonight. 

The slope of IMC-F is larger in the 15 Watt lockloss than the 10 Watts ones.  A trend of IMC F and arm transmission from last night shows there are some inflection points in the slope of IMC F, although these don't corespond to changes in input power or changes in the state of the tidal state machine.

The other 4 locklosses that I looked at were not due to the IMC VCO, and I didn't come up with any good explanation for them.  One notable feature in all of the others is the half a hertx oscillation in the ITM oplev damping loops, that starts when the power increased to 21 Watts, but it doesn't seem like this was the cause of the lockloss. 

Images attached to this comment
sheila.dwyer@LIGO.ORG - 22:45, Wednesday 27 May 2015 (18657)

Tonight we were able to damp the roll modes with all of these settings, as well as ITMX for which we used -100 dB, bp13.9 (FM3+FM4) and a gain of 20.  We also increased the gain for ETMX to 1000

H1 PSL (PSL)
peter.king@LIGO.ORG - posted 05:43, Tuesday 26 May 2015 - last comment - 05:47, Tuesday 26 May 2015(18610)
Laser Trip Causes
The Symptoms
============

The laser is off, the chillers are running and the status screen shows either
"Interlock OK" as red, or both "Interlock OK" and "Epics Alarm" as red.



Possible Causes
===============

a) One of the safety relays in the interlock box is faulty.

b) There is a problem with the TwinCAT code controlling the chillers.

c) There is a problem with the TwinSafe code implementation.

d) Network delays in the PSL EtherCAT network accumulate to a point where
TwinSafe initiates a shutdown.

e) The turbine based flow sensor in the chiller gets stuck, registering a drop
in flow which in turn triggers the laser interlock.



The Evidence
============

a) The Dold LG5929 safety relay extension module has a mechanical life time of
20 million switching cycles and a mean time to dangerous failure of 144.3 years.
The contacts are normally open.

    Safety relays fail, they do not fail intermittently.

    Simulating an interlock box failure by switching off the interlock box
results in a sea of red on the status screen.

b) I have gone through the TwinCAT code for both chillers.  The only difference
is that there is an extra variable declared for the diode chiller.  However this
variable is never invoked in the chiller code.  The instruction sets for both the
diode and crystal chiller are the same.

c) I have gone through the TwinSafe function blocks and have not found anything
wrong with it.

d) This possibility game up because each time the laser had tripped, Patrick and
I noticed that there was 1 lost frame in the TwinCAT datastream.  However with
the laser running last week I noticed that something like 201 frames were lost
and the laser was still running.  So network delays were ruled out.

    Simulating a network delay by removing either the Rx or Tx fibre from the
Ethernet switch, results in a sea of red on the status screen.

e) The output of the flow rate sensor goes to the chiller controller via a normally
open switch.  If the flow rate is within the allowed range, the switch remains closed.
If it goes out of range, it opens and remains open until the flow rate is restored.

    For the crystal chiller, opening the flow rate switch does indeed switch off the
chiller.  Closing the flow rate switch does not switch the chiller back on automatically.
A number of fields on the status screen go red and can only be cleared by switching
the chiller back on and pressing the reset button on the status screen.

    For the diode chiller, opening the flow rate switch does switch off the chiller.
Closing the flow rate switch, turns the chiller back on.  What's more all the red
flags on the status screen go green automatically except "Interlock OK".



Conclusion
==========

Of the 5 cases outlined above, the one that seems to reproduce the observed events
is the last one.  In particular it seems that it is the flow rate sensor in the diode
chiller.
Comments related to this report
peter.king@LIGO.ORG - 05:45, Tuesday 26 May 2015 (18611)
One could well ask why the diode chiller and not the crystal chiller.  It might be
that the diode chiller, having to cool the pump diode heatsinks, may have more
accumulated particulate matter (gold flakes).  We should inspect the filter(s) at
the back of the chiller for any obvious signs of gold, or other stuff.
peter.king@LIGO.ORG - 05:47, Tuesday 26 May 2015 (18612)
The answer I received from Termotek was that the behaviour of the diode and crystal
chillers are indeed different when it comes to recovering from the flow switch opening.
Just in case I mis-understood their reply, I have a clarification e-mail pending.
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