Displaying reports 64941-64960 of 85472.Go to page Start 3244 3245 3246 3247 3248 3249 3250 3251 3252 End
Reports until 00:20, Tuesday 01 September 2015
H1 ISC
sheila.dwyer@LIGO.ORG - posted 00:20, Tuesday 01 September 2015 - last comment - 01:20, Tuesday 01 September 2015(21073)
recycling gain during lock acquistion

At LLO there are problems with engaging the PRC2 ASC loop when the recycling gain is low, but we don't seem to have this problem at LHO.  One theorey about the difference could be that we just arrive in lock with a higher recycling gain.  Although I believed this myself, the data I downloaded from the first 13 days of ER8 seem to indicate this is not the difference.  I looked at times when we first arrived on resonance (112 examples), when we transition to DC readout (after the ASC including soft loops has been on for about 1 minute, 85 examples), and after we power up to the maximum available power (60 examples).

Images attached to this report
Comments related to this report
daniel.sigg@LIGO.ORG - 01:20, Tuesday 01 September 2015 (21082)

The recycling gain corresponding to a critically matched carrier TEM00 is at ~33.5. The successful plots show 32.5 as the lowest value. One might conclude that we typically arrive at the over-coupled case after initial lock. However, the conclusion that the wavefront sensor sign flips at the critically matched point is only true, if we neglect mode matching. If the incoming beam is larger than the cavity beam, the second order mode will support the over-coupled case, whereas a small incoming beam will reduce it.

H1 General (CDS, SUS)
cheryl.vorvick@LIGO.ORG - posted 00:07, Tuesday 01 September 2015 (21080)
EVE OPS Summary: OWL shift canceled - SR3 verified to be still glitchy

SR3 is still glitching - IFO did relock a few times, enough to verify that the porblem is not fixed.

OWL shift called off - Jim was OWL OPS, but staying home.

Sheila, Jenne, Anamaria - staying to make alogs.

H1 SUS (CDS, SUS)
cheryl.vorvick@LIGO.ORG - posted 22:46, Monday 31 August 2015 - last comment - 23:52, Monday 31 August 2015(21077)
EVE OPS shift: the story so far, and current plans

shift started with PRM satellite box swaps (8/31 23:00 - 9/1 00:10UTC, one hour)

 

relocking issues: 9/1 00:10UTC to 5:14UTC

- alignment that I corrected without a full realignment (9/1 ended 1:00UTC)

- delays by BS ISI being tripped - happened twice (ended 2:14UTC)

- delayed by SR3 glitching, preventing IFO from going to CARM_5PM (2:14UTC to 5:14UTC)

 

Having called Vern, Richard, Dave: 5:14UTC

 

Dave restarted h1nds1, so it's back

- option later tonight is to power cycle the computer and then log in and restart the process

Richard

- options are to power cycle AI chassis and or coil drivers for SR3

- and then change the coil driver if power cycle doesn't work

Vern

- ok to call off PWL shift if no SR3 fix and therefore no locking 

- have emailed Jim who's on OWLs, to let him know

 

Currently:

Sheila and Jenne out to LVEA to power cycle AI chassis and coil driver on SR3 (5:46UTC)

Comments related to this report
cheryl.vorvick@LIGO.ORG - 23:31, Monday 31 August 2015 (21078)

rebooted AI and coil driver - no fix

- no change

 

powering off AI for a few minutes 6:08:11UTC

- voltmon power spectra shows T2 noise is now gone

 

AI chassis swapped out 6:24UTC

- SR3 looks better, going to CARM_10PM to look at it there

cheryl.vorvick@LIGO.ORG - 23:52, Monday 31 August 2015 (21079)

Anamaria's comment about voltmon:

when moving SR3 at DC using the alignment sliders we see 1urad of pitch on M0 shows up as 0.5 urad pitch of oplev and 2 cts of voltmon.

H1 CDS (DAQ)
david.barker@LIGO.ORG - posted 22:33, Monday 31 August 2015 - last comment - 22:37, Monday 31 August 2015(21075)
h1nds1 continues to be unstable

h1nds1 daqd process stopped running at 21:47 this evening

computer did not lock up. I logged in and started the process but it quickly stopped again.

I restarted a second time and now it is running. Investigation is continuing.

Monit is not restarting the process, as root I started with /etc/init.d/daqd_nds1 start

Comments related to this report
david.barker@LIGO.ORG - 22:37, Monday 31 August 2015 (21076)

If h1nds1 stops running overnight and will not restart itself we have two options:

  1. switch over to using h1nds0 as your NDS server (this is not the default, so you will have to force your client to use this)
  2. reboot h1nds1 computer by going into the MSR and pressing the RESET switch on the front panel. Computer is clearly marked and is in the 5th rack from far wall.
H1 CDS
cheryl.vorvick@LIGO.ORG - posted 22:09, Monday 31 August 2015 (21074)
H1 update: SR3 glitching - IFO can't make it past CARM_5PM - h1nds1 is white
H1 DetChar (DetChar)
giacomo.ciani@LIGO.ORG - posted 20:54, Monday 31 August 2015 (21072)
August 27th to 30th DQ shift

My detailed DQ shift report for August 27th - 30th can be found here:

https://wiki.ligo.org/DetChar/DataQuality/DQShiftLHO20150827

Highlights:

Main oustanding issues:

In addition, many glitches picked up by Omicron or similar tools could use some further investigation, that I did not have the time to perform. I plan on following up on a few of them in the coming days.

H1 ISC (DetChar)
christopher.wipf@LIGO.ORG - posted 20:45, Monday 31 August 2015 (21070)
Pringled actuator noise in meters

The "noisemon pringle" actuator noise measurement from LLO alog 19853 has been calibrated to meters, and extended to the L1 and L2 stages of all test masses.

Total noise from these stages is estimated to be ~1e-20 m/rtHz around 30 Hz.  This includes driver noise, DAC noise, and glitches (to the extent they were present during the measurement).

A hierarchical noise budget PDF is attached. Here's how things look for ITMX L2:

From this plot you can see the following:

The calibration of these signals is approximate, based on the coil driver and suspension models -- not the precise measurements people have been taking during the past week. There may be some discrepancies especially in the L1 (UIM) stage.  The ETMY L1 plot definitely shouldn't be trusted, because its noisemons appear to be broken (see attached plot).

Scripts have been checked in to the NoiseBudget SVN.

Images attached to this report
Non-image files attached to this report
H1 General
nutsinee.kijbunchoo@LIGO.ORG - posted 18:38, Monday 31 August 2015 (21069)
Day Ops Summary

(All time in UTC)

15:00 Jim has been having trouble locking DRMI all night. So I work on PRMI.

15:32 Managed to get pass DRMI_LOCKED, lockloss at REDUCE_CARM_OFFSET. Saturation alarm complained about PRM.

16:17 Hugh to end stations

16:29 Robert to CER and LVEA

16:40 SR3 is totally unresponsive to Gurdian. See alog 21057.

          DAC recalibratio and DAC restart.

16:53 Hugh back

17:05 Robert back

17:45 Begin initial alignment after several locklosses at random places.

          burtrestored the alignment to last night lock

18:20 Karen/crew to change room and optics lab for cleaning.

19:36 Since there's an operator training going on, Evan insisted I switch the Operating Mode to TRAIN.

21:39 Jeff/Evan to restart PR3, PRM satellite amplifier.

22:00 Jeff back

22:26 Gerado to LVEA hunting for parts.

22:28 Jeff K. brings IMC_LOCK Guardian to OFFLINE

22:39 Gerado back

H1 SUS
betsy.weaver@LIGO.ORG - posted 18:05, Monday 31 August 2015 (21067)
PRM RT/SD and PR3 T1/T2 Status

This afternoon, Richard and Fil tried various hardware diagnostics of the cabling and boxes out on the floor for the shared PRM/PR3 chain noise.  While swapping sat boxes and reterminating cables a few times, the PRM RT TOP BOSEM flopped between flatlining, or being super noisy multiple times after they made connections.  There was additional confusion in the fact that the PRM misaligned state moves the PRM a huge amount in YAW, thus sending the RT BOSEM signal to near zero - we thought this meant it "died" a few times during our troubleshooting.  Long story short, the troubleshooting of the electronics this afternoon didn't seem to improve the noise much.

To be continued...

Images attached to this report
H1 CAL (CAL)
craig.cahillane@LIGO.ORG - posted 17:37, Monday 31 August 2015 (21065)
Strain Uncertainty Carpet Plots Developments
C. Cahillane, D, Tuyenbayev, E, Hall

I have discovered the difference between Plot 1 and Plot 7 in aLOG 20974.
To recap, Plot 1 was strain uncertainty calculated from actual ER7 data, and Plot 7 was strain uncertainty calculated from sensing, digital, and actuation transfer functions only.
One issue was the dewhitening filters were incorrect.  Evan taught me to locate the correct filters based on the GPS times and channel names.  (They can be found in /opt/rtcds/lho/h1/chans/filter_archive/h1calcs/  The shortcut terminal command is "chans")
Another issue was I was using only the ASD of DARM_ERR and DARM_CTRL for my calculations, and ignoring the phase information.  I have corrected this in my code, but not in my uncertainty document T1400586.

Below I have replotted the carpet plots from aLOG 20974 in the same order.  Now you can see very good agreement between New Plot 1 and New Plot 7.
The next step is to discover why the data is so glitchy at high frequency.  I believe it is due to interpolation of the data to fit our ER7 transfer function frequency vector.  
Darkhan has been working on the ER8 DARM model and has made every element into an LTI object.  This will make getting the ER8 transfer functions into any frequency vector very easy, so this is the next step for this project.

The step after that is to begin calculating the error bars themselves. I will have to revisit my Mathematica notebooks to recalculate uncertainty in strain magnitude σ_{|h|} and strain phase σ_{φ_h} with phase info from DARM_ERR and DARM_CTRL included.
Non-image files attached to this report
LHO VE (VE)
gerardo.moreno@LIGO.ORG - posted 17:33, Monday 31 August 2015 (21066)
BSC09 Annulus Ion Pump Fails

Noticed HVE-EX:75IPBSC9_511LOG red on the vacuum main screen, the ion pump appears to have railed around 12:51 pm today.  I drove to End X and found the ion pump connected and powered on, controller shows all LEDs on.

Attached is 1 day trend data.

Non-image files attached to this report
H1 SUS
nutsinee.kijbunchoo@LIGO.ORG - posted 17:18, Monday 31 August 2015 - last comment - 18:12, Monday 31 August 2015(21062)
SR3 noisy/glitchy since last night

J. Kissel, Nutsinee

Dan found glitches in SR3 T2  last night and it seems like we have been having trouble locking ever since so we investgated. SR3 T2 problem started right before Aug 31 09:23 lockloss and never go away. DAC recalibration this morning didn't solve the issue and the power glitch didn't cause it. The noisy/glitchy feature looks just like what happened before the drive swap back in Aug 18.

Images attached to this report
Comments related to this report
nutsinee.kijbunchoo@LIGO.ORG - 18:12, Monday 31 August 2015 (21068)

We brought the SR3 to SAFE for a few minutes. The width of the noise still looks the same but the glitches were gone. This implies that the glitches come from the actuator. These glitches don't seems to appear in MASTER_OUT or NOISEMON channels but they do appear in the witness channels. The first plot is the SR3 T2 before we brought it to SAFE, second plot is after SAFE, and the third plot is 15 minutes before 09:23 lockloss.

Images attached to this comment
H1 CDS
david.barker@LIGO.ORG - posted 17:09, Monday 31 August 2015 (21064)
SITEMAP modified to add two new MAIN catagories: SEI and O-1

The LHO SITEMAP MEDM was modified to add two new MAIN catagories: generic seismic (SEI) and Observing Run related screens (O-1).

I have added Hugo's generic SEI_SAT_OVERVIEW to the SEI button. I have added my new H1CDS_O1_OVERVIEW_CUST to the O-1 list. The new CDS OVERVIEW MEDM must always be GREEN. Any deviation from the O1 configuration will show as RED. Hopefully nothing will be red for long on this screen during O1.

Images attached to this report
H1 CDS (DAQ)
david.barker@LIGO.ORG - posted 16:30, Monday 31 August 2015 (21061)
h1nds1 restarted itself again.

h1nds1 (the default NDS) daqd process died this afternoon. This was a more drastic failure, the computer locked up and had to be reset. The last messages in the log files are different from yesterday to today:

Sunday 30 Aug 15:29:

Retry expired; requesting again

....

Packet buffer is full

Moday 31st Aug 15:58:

[date-time] Ask for retransmission of 15 packets; port 7097

....

Have to skip 15 packets (packet buffer limit exceeded)

H1 CDS (SUS)
david.barker@LIGO.ORG - posted 16:20, Monday 31 August 2015 - last comment - 17:31, Monday 31 August 2015(21060)
SUS IOP restarts to recalibrate 18bit DACs

The times of the restarts of h1sush2a and h1sush56 are summarized below.

2015_08_31 09:13 h1iopsush2a
2015_08_31 09:15 h1susmc1
2015_08_31 09:15 h1susmc3
2015_08_31 09:15 h1suspr3
2015_08_31 09:15 h1susprm
2015_08_31 10:09 h1iopsush56
2015_08_31 10:09 h1susomc
2015_08_31 10:09 h1sussr3
2015_08_31 10:09 h1sussrm

Comments related to this report
jeffrey.kissel@LIGO.ORG - 17:31, Monday 31 August 2015 (21063)SUS
For the record, the above mentioned DAC recalibrations did NOT solve any of the problems that have reared up over the weekend. I can, however, report that the auto-calibration was successful for all DAC cards that were restarted.

The 3rd DAC card's calibration on h1sush2a succeeded slowly, as it has done previously both on Aug 03 2015 (LHO aLOG 20165), and the time prior, Jun 09 2015 (LHO aLOG 19030). As reported before, this DAC card controls PRM M1 RT and SD. Last six channels are PR3 M1 T1, T2, T3, LF, RT, SD. Also as reported before, we don't know what this means or if it is significant.

HOWEVER, according to what tests we have done, this DAC card being slow is merely coincidental with the problems we've been having with the PRM LF RT and PR3 T1 T2 noise found on those OSEM sensors. We've confirmed this by measuring the ASD of the OSEM sensors (as Evan has done in LHO aLOG 21056) with the suspension in SAFE (i.e. no requested drive) and found the noise as expected. We then switched the TEST/COIL enable switch to removed the DAC's ability to drive by removing the DAC input to the coil driver. The noise remained.

The investigation continues...

For h1sush2a (which houses MC1, MC3, PRM, and PR3):
[8808794.054622] h1iopsush2a: DAC AUTOCAL SUCCESS in 5344 milliseconds 
[8808799.414955] h1iopsush2a: DAC AUTOCAL SUCCESS in 5344 milliseconds 
[8808806.438391] h1iopsush2a: DAC AUTOCAL SUCCESS in 6572 milliseconds 
[8808811.798720] h1iopsush2a: DAC AUTOCAL SUCCESS in 5344 milliseconds 
[8808817.586599] h1iopsush2a: DAC AUTOCAL SUCCESS in 5344 milliseconds 
[8808822.947012] h1iopsush2a: DAC AUTOCAL SUCCESS in 5345 milliseconds 
[8808828.307368] h1iopsush2a: DAC AUTOCAL SUCCESS in 5344 milliseconds 
the last time these DACs were recalibrated was Aug 03 2015.


For h1sush2a (which houses SRM, SR3, and OMC):
[5345389.136545] h1iopsush56: DAC AUTOCAL SUCCESS in 5333 milliseconds 
[5345394.496918] h1iopsush56: DAC AUTOCAL SUCCESS in 5344 milliseconds 
[5345400.284896] h1iopsush56: DAC AUTOCAL SUCCESS in 5341 milliseconds 
[5345405.645225] h1iopsush56: DAC AUTOCAL SUCCESS in 5344 milliseconds 
[5345411.433249] h1iopsush56: DAC AUTOCAL SUCCESS in 5341 milliseconds
the last time these DACs were recalibrated was Aug 18 2015 (LHO aLOG 20631)
H1 CAL (CDS)
jeffrey.kissel@LIGO.ORG - posted 13:30, Thursday 27 August 2015 - last comment - 17:28, Monday 31 August 2015(20958)
IFO Taken down to take LSC and END SUS DAC DuoTone Timing Checks
J. Kissel, K. Kawabe, S. Karki

We've broken observation mode such that we can enable the DAC DuoTone timing readbacks on the front ends that are responsible for DARM control, i.e. h1lsc0, h1susex, and h1susey. We needed to take the IFO down for this because the last channel on the first DAC cards for the end station SUS are used for top-mass OSEMs for damping the suspensions. If the damping loops get a two sign waves at 960 and 961 [Hz] instead of the requested control signal for one of the OSEMs, then we get bad news.

Here are the times when the DAC DuoTone switches were ON for the following front ends:

h1susex and h1susey --- 19:04 to 20:04 UTC (12:04 to 13:04 PDT)
h1lsc0 --- 19:16 to 20:06 UTC (12:16 to 13:04 PDT)

Though all relevant channels (ADC_0_30,  ADC_0_31, DAC_0_15) are free on the h1lsc0 front end, we elected to turn the DAC DuoTone off, so that we aren't in danger of an oscillitory analog voltage being sent around the IO chassis that's used to measure the OMC DCPDs.

Data and analysis to come. 

The IFO will be staying down for a few hours, while we finish up some electronics chain characterization of the OMC DCPD analog electronics (along with some other parasitic commissioning measurements).
Comments related to this report
keita.kawabe@LIGO.ORG - 16:24, Thursday 27 August 2015 (20962)

I showed Sudarshan which signal to look at and how to analyze them. He will make an awesome drawing of how things are connected up in this alog.

The first and second attachment shows the duotone timing of the signals pulled from the IOP channels (all 64kHz). The results are summarized in the following table.

Measurement time (UTC)

IOP ADC0 Ch31 (direct) (us) ADC0 Ch30 (loopback) (us) Round-trip (us)
27/08/2015 19:16:11.0 LSC0 7.34 83.78 76.44
SUS_EX 7.25 68.90 61.65
SUS_EY 7.26 68.93 61.67
27/08/2015 22.32:20.0 ISC_EX (PCALX) 7.32 68.93 61.61
ISC_EY (PCALY) 7.26 68.90 61.84

As per yesterday's alog, duotone is about 7.3usec delayed behind LSC ADC, and actually this turned out to be the case for all ADCs.

According to Zuzsa Marka, duotone was "delayed a bit above 6 microseconds compared to the GPS 1pps" (report pending), so probably this means that the ADC timing (i.e. time stamp of ADC) is decent.

Duotone round trip delay for all IOPs except IOP-LSC0 is about 61us or about 4 64k-clock cycles. For LSC0, this was about 5 64k-clock cycles.

I don't know where the difference comes from. This is totally dependent on how the 64kHz ADC input is taken, routed to 64kHz DAC when "DT DAC" bypass switch is in "ON" position (third attachment), and finally output by DAC, but I don't think there should be difference between LSC and everybody else. At least LSC DAC timing doesn't come into the DARM timing.

The next table is for 16kHz pcal channels on the frame. The measurement results as well as the channel names are shown in the last attachment.

UTC user model ADC0 Ch31 (direct in)
(raw, raw-decimation)
loop back Round trip
27/08/2015 22.07.23.0 CAL-PCALX (63.30, 7.37)

ADC0 Ch30 (direct in without AI and AA)
(raw, raw-decimation)
(124.92, 68.99)

61.62
ADC0 Ch28 (with AI and AA)
377.72
 
CAL_PCALY (63.24, 7.31) ADC0 CH30 (direct in without AI and AA)
(raw, raw-decimation)
(124.89, 68.96)
61.65
ADC Ch28 (with AI and AA)
377.07
 

For Ch31 and Ch30, the routing is done bypassing the user model, the signals are merely imported into the user model and decimated.

Sudarshan found the 4x decimation filter delay to be 19.34deg or 55.93us at 960.5Hz, and "raw-decimation" number is obtained by just subtracting this from the raw number. This is consistent with the 64kHz result, so from now on we can look at 16kHz signals as far as pcal is concerned.

I don't know anything about AA and AI, so I'll leave the analysis to Sudarshan.

Relevant scripts and dtt templates are in /ligo/home/keita.kawabe/Cal/Duotone.

Images attached to this comment
sudarshan.karki@LIGO.ORG - 17:28, Monday 31 August 2015 (21043)

Keita's alog explained the timing on Duotone to ADC and DAC to ADC loop as well. Additionally in pcal, channel 28 is routed through the analog AI and AA chasis. The details about how the channels are connected can be found in the attached schematics.

 

From the schematics we can see there are three (3) 4X decimation filters (two downsampling and one upsampling) in this particular chain (Channel 28). This amounts 3*55.93 us = 167.79 us of delay (each of these filter produce phase delay of 19.34deg or 55.93us at 960.5Hz). The analog AA and AI chassis produce phase delay of 13.76  degrees which amounts to about  39.82 us at 960.5 Hz from each chassis totaling in 79.64 us of time delay.

Total Delay = 3*55.93+2*39.82 =247.73 us.

Column 3  contains the measured (raw) time delay and "raw- total delay".

Column 4 contains the roundtrip time (raw-timedelay-7 us) = ~ 122 us (8-64 KHz cycle).

UTC Channel ADC CH 28 LOOP BACK (FILT DUOTONE) Round trip
27/08/2015 22.07.23.0
CAL_PCALX

ADC0 Ch28 (with AI and AA)

(raw, raw-(3*decimation+2*analog AA/AI))

(377.72, 130.29)

 122.92
CAL_PCALY

ADC Ch28 (with AI and AA)

(raw, raw-(3*decimation+2*analog AA/AI))

(377.07, 129.64)

 122.33
 

 

UTC user model ADC0 Ch31 (direct in)
(raw, raw-decimation)
loop back Round trip
27/08/2015 22.07.23.0 CAL-PCALX (63.30, 7.37)

ADC0 Ch30 (direct in without AI and AA)
(raw, raw-decimation)
(124.92, 68.99)

61.62
ADC0 Ch28 (with AI and AA)
377.72
 
CAL_PCALY (63.24, 7.31) ADC0 CH30 (direct in without AI and AA)
(raw, raw-decimation)
(124.89, 68.96)
61.65
ADC Ch28 (with AI and AA)
377.07
 
 
Images attached to this comment
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