The H1 PSL models for ISS and FSS were fixed to replace H2 IPC parts with H1. These models were recompiled and restarted on h1psl0. The IRIG-B cable for h1psl0 was moved back to its original position on the MSR IRIG-B unit at the same time.
The h1susauxh23 system had timing errors, I restarted this system.
Mark Barton, Fred Raab, Szymon Steplewski While trying to test the L2 OSEMs on ETMY and ITMY I noticed that the power spectrum data in DTT was looking very strange for certain combinations of Low Freq, High Freq, and BW. Sometimes the power spectrum plot would show several enormous spikes repeated through the range, while other times nothing would show up. In Diagnostic Test Tools the user has an option to set the low frequency, high frequency, and BW. When I set these to low freq = 0 Hz, high freq = 10 Hz, and BW = 0.05 Hz, DTT returns some strange power spectra data, despite having normal looking time series data. Also using a BW >= 0.05 Hz (corresponding to <=20 seconds of time data) results in 16 seconds of time series data plotted in the DTT time series window, while BW <= 0.05 Hz brings in 32 seconds of data, which seems problematic. Another issue that I am seeing comes from using 50% overlap in the measurement window. Setting the BW = 0.01 Hz (corresponding to 100 seconds of time data) reads in 128 seconds of time series data with 64 seconds overlap, not the 100 seconds of data with 50 second overlap that I expect. Although we came up with evidence of this bug, we don't really know what is causing it to happen for this combination of settings. I have reported the bug at: https://bugzilla.ligo-wa.caltech.edu/bugzilla/show_bug.cgi?id=389
BSC6 annulus at rough vacuum -> valved-in aux pump cart to BSC6 annulus @ ~1515 hrs. local. Also, energized BSC6 annulus ion pump.
Cleanroom was moved over chambers and bolts were broken on all but one door.
The pdf file shows a log/log plot of the pumpdown of initial LIGO BSCs and the advanced LIGO BSC 8 in the LVEA as well as the current one at the yend. The BSC 8 pumpdown is below the others most likely because there were several days of pumping not accounted for before the broken feedthrough was replaced. The BSC 8 pumpdown is besides also anomolously fast. The pumpdown curve for the current advanced LIGO at the yend shows a somewhat smaller exponent n<1 P(t) ~ 1/t^n where t is the time. The areas for the yend pumpdown are: BSC chamber = 5.2 e 5 cm^2 ISI = 1.2 e 6 Quad = 2.3 e 5 Transmon = 1.6 e 5 there are two BSC chambers being pumped together one having the advanced LIGO components and the other the initial LIGO components. The total area is 2.7 e 6 cm^2. Using the empirical Dayton relation for water outgassing, the outgassing rate varies as J(300K) = 1.7e-7/t(hours) torr liters/sec/cm^2/hour. The predicted water vapor flow is then 4.6 e-1/t(hrs) torr liters/sec/hour. Assuming 1500 liters/sec for the turbo pump speed, the pressure of water after 10 days is estimated as 1.3 e -6 torr. Not a hugh amount different than an extrapolation of the data would indicate. In summary, the slow pumpdown is unfortunately to be expected had we only put the known numbers into a calculation before hand. The question now becomes how to best deal with this.
Wipe down was completed early this morning and second vacuum quickly followed. Once the dust barriers were removed, Robert S. went into the chamber to access BSC3 and perform some test with regard to the black residue (the material formerly known as "re-oxidation") left from Chamber Cleaning. After lunch, the chamber inspection process was completed and FTIRs were taken. In addition, the dome was documented, welds were vacuumed and wiped,walls were vacuumed, FTIRs were taken and the dome was prepared for re-install. By about 2pm, the dome was ready to fly back to the chamber. The BSC flooring passed FTIR and is wrapped-bagged-tagged and waiting in the VPW for pick up. We expect to install the flooring and then the doors and dome tomorrow.
The first pumpdown of BSC9 with the iLIGO stack.
Same plot but longer. This shows the impact of ~2 weeks of heating by allowing the building temperature to rise to ~90F.
J. Kissel, P. Fritschel Of interest to several on-going investigations, Peter and I took a look at the noise monitor channels for H2 SUS ETMY for the UIM (L1) and PUM (L2) stages. These signals pick off the output of each differential coil driver channel, and convert to a single ended, high-passed monitor signal, with a calibration of Coil Output Noise [V_out/rtHz] = Noise Monitor Signal [ct/rtHz] * ADC Gain [V/ct] * Monitor Board Gain [diff. V_out/ sing. V_mon] where, since the high pass filter is flat by 10 Hz, we've assumed the Monitor Board is only a scale factor. Those gains are ADC Gain = 40 / 2^16 [V/ct] Monitor Board Gain = 392 [Single-ended Volts Out / Differential Volts In] According to the design studies [UIM = T0900233; PUM = T0900277], the output noise of the coil driver should be around, (Equivalent Current Noise) * (Out Resistors + Coil Impedance) = (Output Voltage Noise) (across the coil [A/rtHz]) ( [V/A] ) ( [V/rtHz] (@ 10 Hz) ) UIM: 2e-12 * 7.84e3 = 1.5e-8 PUM: 2.3e-12 * 4.42e3 = 1.0e-8 in the lowest noise modes. Note that this is what Ron Cutler calls the "component noise," which we traditionally call the "coil driver noise," or "output referred noise" the self-noise of the coil-driver due to the resistors, op-amps, etc. on the board. What he calls the "input noise specification" is the DAC noise, which is claimed to be 100 [nV/rtHz]. We see from the results attached, the results are more like 100 nV/rtHz. However, this was measured in the "acquire" modes of each driver, so we expect the noise to be basically the same as the noise input to the driver, i.e. the DAC noise, which we indeed expect to be about 100 nV/rtHz.
J. Kissel, P. Fritschel
We've since measured the noise in the lowest noise modes,
UIM: with all low-pass (LP) filters ON (i.e. setting the UIM BIO State Request to 4.0)
PUM: with acquire (Acq) bit OFF and and low-pass (LP) ON (i.e. setting the PUM BIO State Request to 3.0)
(with both COIL/TEST Enable bits set to 1.0)
and the results are more like what's expected from the design studies
(Measured Output Referred Noise)
( Lowest Noise Mode )
( [V_out/rtHz] @ 10 Hz )
UIM: ~1.5e-8
PUM: ~1.5e-8
Unlike the earlier measured noise, the input DAC noise is filtered down by some factors, so the "component noise," the self-noise of the resistors, op-amps, etc. is "exposed."
- For the UIM, the input/DAC noise is squashed by 3 10Hz low pass filters, so the dominant noise is the coil-driver, component self noise at all frequencies (above 10 Hz). One can just barely see a little bump creeping in around 300 Hz from the DAC noise, which is from the [z:p]=[60:325] frequency response inherent to the output stage.
- For the PUM, the DAC noise is only filtered out in the region around 10-20 Hz (in the "tough" region where the SUS noise is potentially dominant in the DARM spectra), but otherwise rolls back up according to the [z:p] = [13:130] frequency response inherent to the output stage (with the Acq bit OFF), so at high frequency the output noise re-asymptotes to 100 [nV/rtHz].
A couple of other things to notice when comparing the above data with this data:
- In the UIM driver, whose output noise is dominated by DAC noise in Acq mode, and Component Noise in Low Noise mode, one can clearly see 60Hz lines in the Component Noise.
- The spikes in the PUM output noise have shifted in frequency, and are not 60 Hz lines... not sure what that means or why.
This data can be found committed to the SusSVN repository here: /ligo/svncommon/SusSVN/sus/trunk/QUAD/H2/ETMY/Common/Data/ 2012-06-12_H2SUSETMY_L1L2_NoiseMon.pdf [first attachment] 2012-06-12_H2SUSETMY_L1L2_NoiseMon.xml [first measurement] 2012-06-12_H2SUSETMY_L1L2_NoiseMon_LowestNoiseModes.pdf [second attachment] 2012-06-12_H2SUSETMY_L1L2_NoiseMon_LowestNoiseModes.xml [second measurement] where the "*LowestNoiseModes.xml" has the first measurement as references.
J. Kissel Another measurement for these two driver to facilitate on-going electronics studies: leaving both drivers in low noise mode (UIM: LP1, LP2, LP3 all ON; PUM: Acq OFF, LP ON), but switching between the COIL In (connected to the AI/DAC) and TEST In (assumed to be an open DB9 connector). Attached are the results. You'll notice that there are is no change in the noise floor between the two states on the UIM driver, but for the PUM the four channels get totally different noise (from the COIL In state, and from each other). What did we expect? It's a long story (eventually, the story will be told in L1200193), but in short: - Each coil driver board (yes, all of them) has a equi-potential voltage reference plane to which on-board components are grounded (called "0V" on the schematic). - The given coil driver chassis forms a second equi-potential plane (which we'll call "ground" for now) - The "0V" reference plane is connected internally to pin 5 of both the "COIL In" and "TEST In" DB9 connections (called "DEMANDS" and "Front Panel Test Inputs" on the schematics), as well as to several of the output pins. - External to the chassis, the system wiring diagrams (yes, all of them) show that all of these pins are shown to be "NC" or "not connected" to cables going to and from these chassis. - It's unclear *how* they are not connected: is the pin is shorted to the chassis, to the backshell, or maybe the cable doesn't have a pin in it's female socket ... could be any number of things. - In the as-measured configuration of the electronics, the "COIL In" DB9 is connected to the full signal chain as shown in the system wiring diagram (D1002741); the "TEST In" DB9 is open to air (and not shown in D1002741). - In general, the chassis "ground" is free to swing with the surrounding environment, whose changing electric field can then interact with the reference ground "0V" on the boards, and also interact with the the components on the board. - IF and ONLY IF the differential paths are identical (which, in the real world is not possible because of component tolerances), this changing field would be common-mode to the two positive and negative paths, and cancel. - However, IF the paths are not perfectly the same, the common-mode surrounding field will couple differentially to the components and cause noise for various reasons. The HOPE was that there was no such coupling between the "0V" reference plane and the "ground" plane of the chassis going on, the switch between "COIL In" and "TEST In" would merely remove the (filtered) 100 [nV/rtHz] Input DAC noise, and we could therefore measure the component, self-noise of the board at the output. For the UIM board, the noise level remained roughly the same. We expected the noise in the "COIL In" configuration to be dominated by the component noise, so if we've "turned off" the DAC noise by switching to the TEST In configuration, we indeed expect no change. GOOD! For the PUM board, the DAC noise was not filtered as much as the UIM board in the lowest noise mode and is therefore dominant, so we expected to see the noise on all channels to simultaneously drop to the component, self-noise noise level when switching to "TEST In." Instead we see what's shown -- each channels noise is differently elevated, and its frequency response has changed. I don't want to make claims just yet of exactly what's happening (which is why I said "for various reasons), but the proposal L1200193 will suggest what to do next. Weeeeeee-ew. How do you say ... l'enquête se poursuit!
This appears to be the first pumpdown of BSC10 in 2000.
[Jeff B, Travis S, Andres R, Gerardo2 M] Today we moved the HLTS PR3 from the test stand in the Staging Building to the LVEA. This is the first of the Hanford Triple suspensions to be moved to the LVEA. We need to make some minor adjustments to our lifting gear for future HxTS moves, but in general, things went smoothly and with no serious problems encountered. Gross weight of PR3, without vibration absorbers, is 210lbs.
PSL had a need to access a particular feedthru for their In-Vacuum Cable runs. Although the LHAM2 layout managed to reflect this it did not get propagated to LHO documents. So we had to swap the feedthrus on D2 & D5. The layout is D1002873. Version v6 shows how we initially installed them. In v7 there is a text file to the effect of the change but the layout itself is not yet updated. There are two open ports now on D5 as these take 5-way Coax. These Feedthrus are in C&B now and I hope we can get these on before the next pump down.
Tomorrow Barker & Columbia will take H2 down for timing work
6 days of turbo pumping, pressure @ 2x10-6 torr, scan attached.
Work permits pulled for In-Chamber Cleaning.
First vacuum and wipe-down are complete. Second vacuum is likely to be completed by the end of the day. We expect to complete work in the dome by lunch tomorrow. We anticipate FTIR results for the permanent flooring either today or tomorrow. If all goes well, we may be out of BSC1 (including dome and door replacement) by tomorrow afternoon.
Yesterday Keita and I found that the output of the ALS PLL Phase-Frequency Discriminator unit was noisy and oscillating between its voltage rails. We traced the problem back to a very noisy output signal from the frequency divider which provides the LO to the P-F Discriminator board. Going up the chain, we found that the frequency divider unit was getting 0dBm instead of the nominal 13 dBm from the VCO unit. Apparently the VCO unit is not working properly. We removed it from the rack and took it to the corner station for inspection. We are going to check it inside to find the cause of the mismatched power levels.
Paul Schwinberg checked the board in the EE shop and found that the RF levels were actually correct. It's not clear why the board was malfunctioning when Keita and I measured the levels on Friday. We took the board to the end station and reinstalled it back into the rack. This time the output level was okay: about +13 dBm.