aLIGO LHO Logbook

H1 CDS - CDS slow filesystem and not all services are back online

david.barker@ligo.org — Thu, 04 Dec 2025 22:36:44 -0800

Author: david.barker@ligo.org

Report ID: 88376

Recovery of the front end systems was hampered by a slow /opt/rtcds file system, which still persists. There are no logs on h1fs0 indicating the problem, and the ZFS file system itself appears to be fully functional. Hourly backups by h1fs1 continue normally. At this point we cannot rule out a network issue.

The alarms system is running but does not seem to be operational, again no errors are being logged and channel access appears to be working.

Jim reported a bad model initialization with its safe.snap, most probably caused by a slow /opt/rtcds. I had to restart many models several times to get through a "burt restore" timeout for similar reasons.

We may need to restart h1fs0 in the morning and remount /opt/rtcds on all the NFS clients

Images attached to this report

H1 CDS - Power Supply Failure for EY SUS-C1/C2 Racks

filiberto.clara@ligo.org — Thu, 04 Dec 2025 22:01:32 -0800

Author: filiberto.clara@ligo.org

Report ID: 88375

The positive 18V power supply which provides power to Rack SUS-C1 and SUS-C2 failed after the power outage. Fan seized and power supply tripped off. Power supply was replaced.

New Power Supply installed - S1300291

F. Clara, M. Pirello

SUS

H1 DAQ - EtherCAT Corner Station Chassis 4

filiberto.clara@ligo.org — Thu, 04 Dec 2025 21:48:58 -0800

Author: filiberto.clara@ligo.org

Report ID: 88374

WP 12915
Corner Station Controls Chassis 4 Wiring Diagram - E1101222
EtherCAT Corner Station Chassis 4 - D1101266
Modifications to the Beckhoff chassis - E2000499

The EtherCAT Corner Station Chassis 4 was modified per E2000499. New Beckhoff terminals were installed to support JAC and BHD. A new rear panel was installed to accommodate the new rear adapter boards and shutter control connectors. The din rail power terminal blocks were relocated making the exising power cables too short. New power cables installed to the EtherCAT couplers and power terminals. All field cabling was reconnected, expect for ISC_313. The Beckhoff software will need to be updated.

EtherCAT Corner Station Chassis 4 - Serial Number S1107450

F. Clara, D. Sigg

H1 SEI - Status of SEI recovery

jim.warner@ligo.org — Thu, 04 Dec 2025 20:58:08 -0800

Author: jim.warner@ligo.org

Report ID: 88373

Seems like all of the models are running, but many of the guardians are still down. What I was able to get up and running:

HEPI Pump stations for all 3 buildings. Patrick had to help some with the end station beckhoff. I had to adjust the float switch for the overflow tank at EX, we were ridding just at the trip level there. The corner station Athena looked dead when I powered on the power supply on the mezzanine, but I think some of the leds are just dead. Good thing we plan to replace that soon.

Both BRS are running. Patrick had to power cycle the EX beckhoff, we were then able to restart the software. The damping settings got reverted (highthreshold and lowthreshold), so I had to fix those through the cli. Heater settings also got lost, both brs cooled off a bit over the several hours we were blind, and will take a little while to warm back up. Probably will keep watching for a while to make sure everything is okay, but I think we are good.

Some of the chambers are able to be isolated through guardian, but many have dead guardian nodes. I manually engaged damping where I couldn't get the ISI isolated via guardian.

None of the blend, sensor correction or cps diff is alive enough to recover yet. I have manually disabled sensor correction for the corner, the ends can't be isolated yet. I guess that will wait for tomorrow.

OpsInfo

LHO General - Comment to Thurs DAY Ops Summary

ryan.short@ligo.org — Thu, 04 Dec 2025 19:20:41 -0800

Author: ryan.short@ligo.org

Report ID: 88372

Since Oli's alog, I tried to keep a rough outline of the goings-on:

Marc and Fil went down to EY to replace the failed power supply, which brought life back to the EY frondends.

Dave noticed several models across site had timing errors, so he restarted them.

Gerardo continued to torubleshoot VAC computers at the mid-stations.

Once CDS boots were finished, I brought all suspension Guardians to either ALIGNED or MISALIGNED so that they're damped overnight.

I started to recover some of the Guardian nodes that didn't come up initially. When TJ started the Guardian service earlier, it took a very long time, but most of the nodes came up and he put them into good states for the night. The ones that didn't come up (still white on the GRD overview screen) I've been able to revive with a 'guardctrl restart' command, but I can only do a couple at a time or else the process times out. Even this way, the nodes take several minutes to come online. I got through many of the dead nodes, but I did not finish as I am very tired.

Main things still to do for recovery: (off the top of my head)

Finish reviving dead Guardian nodes
Maybe restart the main file server (Dave suspects this is the cause of general slowness of CDS machines)
Ensure seismic is in a good place
Finish Beckhoff software updates that were in-progress at the time of the outage
Clear up remaining IPC errors across CDS land
Turn lasers back on
Check suspension positions
Lots of other things probably
Thank everyone for their tireless efforts

OpsInfo

H1 SUS - Comment to SUS - power outage recovery

ryan.short@ligo.org — Thu, 04 Dec 2025 18:57:47 -0800

Author: ryan.short@ligo.org

Report ID: 88371

Once CDS reboots were finished, I took all suspensions to either ALIGNED or MISALIGNED so that they're damped overnight.

LHO General - Comment to Thurs DAY Ops Summary

oli.patane@ligo.org — Thu, 04 Dec 2025 18:36:03 -0800

Author: oli.patane@ligo.org

Report ID: 88370

Recovery milestones:
22:02 Power back-up
22:04 CDS / GC seeing what's on/functional, then bring infrastructure back up
22:10 VAC team starts Kebelco to support the ar pressure that's keeping the cornerstation gate valves for closing
22:13 Phones are back
22:17 LHO GC Internet's back
22:25 GC wifi back up, alog and CDS back up
22:40 RyanS, Jason, Patick got PSL beckoff back up
22:55 VAC in LVEA/FCES back up
22:57 CDS back up (only controls)
23:27 PSL computer back
00:14 Safety interlock is back
00:14 HV and ALSY on at EY
00:35 opslogin0 back up
00:37 CS HV back up
00:53 CS HEPI pump station controller back up
01:05 CO2X and CO2Y back up
01:10 HV and ALSY on at EY
01:22 PSL is alive

Note: EY 24MHz oscillator had to be power cycled to resync

Casualties:
- lost ADC on seiH16
- 18V power supply failure at EY in SUS rack

Log:

Start Time	System	Name	Location	Lazer_Haz	Task	Time End
22:32	VAC	Gerardo	MX, EX, MY, EY	n	Bringing back VAC computers	23:41
23:32	VAC	Jordan	LVEA, FCES	n	Bringing back VAC computers	22:55
22:54	PSL	RyanS, Jason	LVEA	n	Turning PSL chiller back on	23:27
23:03	VAC	Jordan	LVEA	n	Checking out VAC computer	23:41
23:56	SAF	Richard	EY	n	Looking at safety system	00:25
00:02	JAC	Jennie	JOAT, OpticsLab	n	Putting components on table	01:24
00:19	SAF	TJ	EX	n	Turning on HV and ALSX	00:49
00:38	TCS	RyanC	LVEA	n	Turning CO2 lasers back on	01:06
01:03	EE	Marc	CER	n	Power cycling io chassis	01:14
01:06	PSL	RyanS, Jason	LVEA	n	Checking makeup air for PSL	01:10
01:07	JAC	Jennie	LVEA	n	Grabbing parts	01:14
01:08	beckhoff	patrick	cr	-	BRSx recovery	02:20
01:08	sei	jim	EX.EY	-	HEPI pump station recovery	01:58
01:25	SEI	Patrick	EX	n	BRSX troubleshooting	01:54
01:27	EE	Marc	EX	n	Looking at RF sources	02:09
02:00	EE	Fil	EY	n	Power cycling SUSEY	02:19
02:09	VAC	Gerardo	MX	N	Troubleshooting VAC computer	02:27
02:12	EE	Marc	CER	N	Checking power supplies	02:16

H1 SUS - SUS - power outage recovery

rahul.kumar@ligo.org — Thu, 04 Dec 2025 18:27:14 -0800

Author: rahul.kumar@ligo.org

Report ID: 88369

Oli, Ryan S, Rahul

Except ETMX and ETMY (timing error, work currently ongoing), we have recovered all other suspensions by un-tripping the WD and setting it to SAFE for tonight. The inmons looks fine - eyeballed them all (bosems and aosem), nothing out of the order.

For ETMX and ETMY, Dave is currently performing a computer restart, following which they will set to safe as well.

SUS

LHO General - Thurs DAY Ops Summary

corey.gray@ligo.org — Thu, 04 Dec 2025 18:02:48 -0800

Author: corey.gray@ligo.org

Report ID: 88350

TITLE: 12/04 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY:

After CDS & H1-Locking work of yesterday, today we transitioned to starting prep work for the upcoming vent of HAM7.

However, there was more CDS work today which was related to ISC Slow Controls....but in the middle of this...

There was a 90min power outage on site!!

LOG:

early-1615 Randy was at the FCES putting stickers on items
1539-1900 pre-vent technical cleaning begins (kim.nellie)
- 1716 SR3 + HAM5 tripped; gave it some time, untripped/redamped @1805
1545 SEI_ENV transitioned to MAINTENANCE for vent
1609 TCSx Laser off (TJ contacted; prob due to cleaning near the rack)
1624-1745 BSC2 platform & then sorting parts (randy)
- Tripped BS, ISI, HEPI---leaving tripped until randy finishes in about an hr
- Once he was done, BS was taken to ALIGNED & SEI_BS taken to DAMPED_HEPI_OFFLINE
- 1745-1845 Sorting through rail parts in North Bay
1626 quick assistance for cleaning (chris)
1628-1635 lvea walkthru (richard)
1630 cer to pull slow control chassis for ISC (fil)
- This affects a PZT for the IMC, so it lost lock. Keeping IMC_LOCK at OFFLINE during this beckhoff work.
1718-1810 Unboxing the JAC in the optics lab (jennie, jason)
1728 Taking Integrating sphere (had been at KAGRA) into PCal Lab (tony)
1730-1855 Grabbing parts at offsite vendor (mitch)
1751-1900 Building 2nd CHETA enclsure in the CHETA/JAC Lab (matt)
1803-2012 OPO Testing cont (KarMeng.Eric)
- 1812 Shiela joining but will be in/out with them + looking for parts
1813-1820 chamber measurements for JAC (jason)
1814 Kobelco (purge air compressor) being turned on (travis,jordan)
1848-2000 Inventory work at EX + EY (randy)
2005 Grabbing wipes in Cleaning Room (ibrahim)
2023 CHETA Viewport part search (gerardo)
2025 Power Outage ON Site!
- Ended up down for over 90min
See oli's alog for a summary of recovery.

Images attached to this report

H1 PSL - PSL Recovered After Power Outage

jason.oberling@ligo.org — Thu, 04 Dec 2025 17:41:21 -0800

Author: jason.oberling@ligo.org

Report ID: 88368

R. Short, P. Thomas, J. Oberling

We have recovered the PSL after today's power outage. Some notes for the future:

When recovering the PSL Beckhoff PC and control software, make sure both Control Boxes are ON before trying to start the software
The PSL's calibration data was lost, again (this seems to happen after every software restart, we're still not sure why)

I've attached a picture of the Settings table for PSL sensor calibration and operating hours for future reference. Again, our persistent operating hours (that track total uptime of PSL laser components; OPHRS A in the attached picture) will continue to be wrong as we cannot update this value. The current operating hours, which tracks operating hours of currently operating components (i.e. we've been running this specific NPRO for X hours; OPHRS in the attached picture) are correct.

We have the PMC and FSS RefCav locked, but have left the ISS OFF overnight while the PMC settles. The PMC requires a beam alignment tweak (normal after an extended time off, like a 90 minute power outage) but we don't yet have Beckhoff so we don't have access to our picomotor mounts. I'll tweak the beam alignment tomorrow once Beckhoff has been recovered.

Images attached to this report

H1 CAL - Comment to Calibration measurement post DAC swap

elenna.capote@ligo.org — Thu, 04 Dec 2025 14:46:00 -0800

Author: elenna.capote@ligo.org

Report ID: 88365

Jeff and I looked over the report and have concluded that the changes we see are very minimal, and do not require any updates to the calibration at this time.

There is a 1% change in the L3 actuation strength, comparing the measurement from 11/18 and 12/04. This could be from the DAC change or it could be from charging. Either way, it is small enough that kappa TST is likely correcting this properly. The overall systematic error is still around 1%, as it was before the DAC change.

We don't think there needs to be any changes to the pydarm ini file at this time.

H1 SQZ - VOPO crystal mount stage test

karmeng.kwan@ligo.org — Thu, 04 Dec 2025 14:32:40 -0800

Author: karmeng.kwan@ligo.org

Report ID: 88364

[Sheila, Eric, Karmeng]

We checked the NLG of the OPO without cavity lock, threshold power is roughly at 3.7mW, at the same order as the test performed at MIT (E2500270)

Checked the crystal alignment, found 9 good dual resonant position, from -2689um to 1223um, with 490um separation between each point. Everything seems to be in a good position.

Plus a clipped dual resonance position at -3190um. Crystal edge is roughly at 1500um and -3200um.

Red alignment does not shift between the various crystal position.

SQZ

LHO General - POWER OUTAGE At LHO At 1225pm PDT!

corey.gray@ligo.org — Thu, 04 Dec 2025 12:29:39 -0800

Author: corey.gray@ligo.org

Report ID: 88363

It's been a few minutes so far. There is emergency lighting. Luckily since it was lunchtime there were no people out on the floor. Recovery Begins!

H1 SEI - Ground Seismometer Mass Position Check - Monthly

ryan.short@ligo.org — Thu, 04 Dec 2025 11:29:19 -0800

Author: ryan.short@ligo.org

Report ID: 88362

FAMIS 38886, last checked in alog88025

Both HAM5 and the BS chambers were in 'ISI_DAMPED_HEPI_OFFLINE' at the time this was run, but all other chambers were nominal.

There are 15 T240 proof masses out of range ( > 0.3 [V] )!
ETMX T240 2 DOF X/U = -1.565 [V]
ETMX T240 2 DOF Y/V = -1.633 [V]
ETMX T240 2 DOF Z/W = -0.886 [V]
ITMX T240 1 DOF X/U = -2.256 [V]
ITMX T240 1 DOF Z/W = 0.467 [V]
ITMX T240 3 DOF X/U = -2.386 [V]
ITMY T240 3 DOF X/U = -1.073 [V]
ITMY T240 3 DOF Z/W = -2.895 [V]
BS T240 1 DOF Y/V = -0.323 [V]
BS T240 2 DOF Z/W = 0.327 [V]
BS T240 3 DOF X/U = -0.547 [V]
BS T240 3 DOF Z/W = -0.401 [V]
HAM8 1 DOF X/U = -0.638 [V]
HAM8 1 DOF Y/V = -0.729 [V]
HAM8 1 DOF Z/W = -1.11 [V]

All other proof masses are within range ( < 0.3 [V] ):
ETMX T240 1 DOF X/U = 0.007 [V]
ETMX T240 1 DOF Y/V = -0.049 [V]
ETMX T240 1 DOF Z/W = -0.017 [V]
ETMX T240 3 DOF X/U = -0.005 [V]
ETMX T240 3 DOF Y/V = -0.056 [V]
ETMX T240 3 DOF Z/W = -0.051 [V]
ETMY T240 1 DOF X/U = 0.045 [V]
ETMY T240 1 DOF Y/V = 0.198 [V]
ETMY T240 1 DOF Z/W = 0.249 [V]
ETMY T240 2 DOF X/U = -0.073 [V]
ETMY T240 2 DOF Y/V = 0.218 [V]
ETMY T240 2 DOF Z/W = 0.037 [V]
ETMY T240 3 DOF X/U = 0.268 [V]
ETMY T240 3 DOF Y/V = 0.076 [V]
ETMY T240 3 DOF Z/W = 0.147 [V]
ITMX T240 1 DOF Y/V = 0.254 [V]
ITMX T240 2 DOF X/U = 0.151 [V]
ITMX T240 2 DOF Y/V = 0.258 [V]
ITMX T240 2 DOF Z/W = 0.223 [V]
ITMX T240 3 DOF Y/V = 0.104 [V]
ITMX T240 3 DOF Z/W = 0.094 [V]
ITMY T240 1 DOF X/U = 0.074 [V]
ITMY T240 1 DOF Y/V = 0.123 [V]
ITMY T240 1 DOF Z/W = -0.013 [V]
ITMY T240 2 DOF X/U = 0.017 [V]
ITMY T240 2 DOF Y/V = 0.22 [V]
ITMY T240 2 DOF Z/W = 0.148 [V]
ITMY T240 3 DOF Y/V = 0.091 [V]
BS T240 1 DOF X/U = 0.184 [V]
BS T240 1 DOF Z/W = -0.223 [V]
BS T240 2 DOF X/U = 0.094 [V]
BS T240 2 DOF Y/V = -0.224 [V]
BS T240 3 DOF Y/V = 0.004 [V]

There are 2 STS proof masses out of range ( > 2.0 [V] )!
STS EY DOF X/U = -4.625 [V]
STS EY DOF Z/W = 2.321 [V]

All other proof masses are within range ( < 2.0 [V] ):
STS A DOF X/U = -0.498 [V]
STS A DOF Y/V = -0.915 [V]
STS A DOF Z/W = -0.485 [V]
STS B DOF X/U = 0.154 [V]
STS B DOF Y/V = 0.939 [V]
STS B DOF Z/W = -0.337 [V]
STS C DOF X/U = -0.685 [V]
STS C DOF Y/V = 0.77 [V]
STS C DOF Z/W = 0.505 [V]
STS EX DOF X/U = -0.195 [V]
STS EX DOF Y/V = -0.111 [V]
STS EX DOF Z/W = 0.112 [V]
STS EY DOF Y/V = 1.271 [V]
STS FC DOF X/U = 0.071 [V]
STS FC DOF Y/V = -1.254 [V]
STS FC DOF Z/W = 0.567 [V]

H1 CAL - Calibration measurement post DAC swap

elenna.capote@ligo.org — Thu, 04 Dec 2025 10:43:31 -0800

Author: elenna.capote@ligo.org

Report ID: 88361

Last night I took a calibration measurement (broadband and simulines) after the IFO was locked for about 3.5 hours. This generated calibration report 20251204T035347Z.

The results from broadband and simulines on the front page look reasonable. The plot label indicates that these are from PCAL X and Y but I think the broadband and simulines are run on PCAL Y only, so I don't know if PCAL X agrees with Y. I believe as of last night, the DAC for PCAL X had been swapped.

I made no changes to the pydarm ini file to account for the DAC change before running the report.

Non-image files attached to this report

H1_calibration_report_20251204T035347Z.pdf

LHO VE - Thu CP1 Fill

david.barker@ligo.org — Thu, 04 Dec 2025 10:36:05 -0800

Author: david.barker@ligo.org

Report ID: 88360

Thu Dec 04 10:15:45 2025 INFO: Fill completed in 15min 42secs

Plot has zoomed y-scale to reduce number of divisions in order to show detail.

Images attached to this report

H1 PSL - PSL Cooling Water pH Test - Monthly

ryan.short@ligo.org — Thu, 04 Dec 2025 10:25:04 -0800

Author: ryan.short@ligo.org

Report ID: 88359

FAMIS 27645

pH of PSL chiller water was measured to be between 10.0 and 10.5 according to the color of the test strip.

H1 ISC - Comment to instructions for recovering alignment after gate valves are excercised

elenna.capote@ligo.org — Thu, 04 Dec 2025 10:24:16 -0800

Author: elenna.capote@ligo.org

Report ID: 88358

Thank you Sheila for writing up this process in very helpful detail.

I wanted to add a few more notes based on many iterations of this process.

#2 and 3 add on: often, if the vent was invasive enough, the other DRMI loops besides SRC ASC may also give some trouble. There are options in the use_DRMI_ASC and use_PRMI_ASC to also disengage PRC1 (PRMI and DRMI), INP1 (DRMI), PRC2 (DRMI) and MICH (PRMI and DRMI). I recommend disengaging PRC1, INP1 and PRC2 if the DRMI ASC is not working well and PRC1 for the PRMI ASC. This will then require moving PRM (PRC1), PR2 (PRC2) and INP1 (IM4) by hand. We rarely disengage MICH. Generally MICH needs to stay on during CARM offset reduction so the beamsplitter can follow DHARD. Also note that SRC2 controls both SRM and SR2, so SR2 may need to be moved as well as SRM.

#4 add on: the DHARD error signal may be very bad if the arms are too far away from resonance, and the error signals can flip sign as the CARM offset is reduced. To make DHARD engagement easier, it might be helpful to step the CARM offset by hand while moving DHARD manually, even taking smaller steps than the guardian code does. Then, DHARD can be engaged. Note: if you find yourself flipping the sign of the DHARD loops to engage them, this is a problem, and you will likely have a lockloss during CARM offset reduction if the DHARD loops are closed with the wrong sign!

#6 and 7 add on: if the alignment is poor enough, it might be necessary to walk the IFO alignment further before engaging the loops in ENGAGE_ASC_FOR_FULL_IFO by putting the guardian code in the terminal. This is the process I follow:

group the loops into CHARD/INP1/PRC2 pitch and yaw
turn off the soft limiters so you can see the full error signal
- I find the full IFO ASC ndscope template useful here: sitemap>LSC>locking>locking scopes>ASC signals
- sitemap>ASC>overview>ASC arm cavities/central part> upper left corner of each loop control block called "[loop]_SMOOTH_ENABLE"
step CHARD using the move_arms_dev.py script, PRC2 with PR2 slider and INP1 with IM4 slider. Start with either pitch or yaw only. These loops are sometimes cross coupled, so you might need to step one and then the other iteratively. Check that as the error signals go to zero the buildups improve (PRG, POP18 and arm power increase, POP90 decrease)
Once the error signals are close to or at zero, use the guardian code to engage their filters and gains to close the loop. Repeat this process for pitch and yaw.
Before closing ADS3, move PRM to bring the ADS error signal close to zero
Then, proceed to move SRM and SR2 to close SRC1 and SRC2. If this doesn't work, leave them open until the soft loops are closed, then try again
You might need to go line by line with the guardian shell for ENGAGE_SOFT_LOOPS. ADS4 and ADS5 control the X arm SOFT and Y arm SOFT dofs respectively. You can also use move_arms_dev.py to steps these dofs closer to zero before closing the loop

I like the recommendation of noting the green camera references throughout the process. If you lose lock before you get a chance to reset the references, you will have to repeat the whole process (alignment does not offload after DRMI!). Jenne's metaphor is that the green references are like video game save points, so noting them throughout the process can be helpful in case a lockloss happens, you can return to where you were before. The final green reference setting should be after all alignment loops are closed (including soft loops!).

Another offset that is useful to reset is the POP A offset. In DRMI, PRC1 runs on the POP A QPD and the alignment is offloaded. If the POP A offsets are set to the PRM's final location in ENGAGE_ASC_FOR_FULL_IFO, the ADS convergence for DOF3 will be much faster, as DRMI will put the PRM where it already needs to be. The convergence of this loops is so slow it sets how long this state takes, which can be many minutes if the PRM is far off from where it needs to be.

LHO General - Comment to Thurs DAY Ops Transition

corey.gray@ligo.org — Thu, 04 Dec 2025 09:47:42 -0800

Author: corey.gray@ligo.org

Report ID: 88357

FYI: Elenna ran a Calibration last night (she noted in Mattermost and files were generated at 818pmPDT).

CAL

H1 CDS - CDS Frontend Upgrade Summary: Thursday 4th December 2025

david.barker@ligo.org — Thu, 04 Dec 2025 09:45:26 -0800

Author: david.barker@ligo.org

Report ID: 88356

Summary of where we are in the upgrade:

h1susey

All Gen Std DACs replaced with 2 LIGO-DACs. All AI-Chassis upgraded to SCSI daisy-chain.

Timing card replaced with one having latest firmware

New models [h1iopsusey, h1susetmy, h1sustmsy, h1susetmypi]

All models running RCG-5.5.2

h1susex

All Gen Std DACs and first-gen LIGO-DAC replaced with 2 LIGO-DACs. All AI-Chassis upgraded to SCSI daily-chain.

Timing card firmware upgraded in place

New models [h1iopsusex, h1susetmx, h1sustmsx, h1susetmxpi]

All models running RCG-5.5.2

h1iscex

18bit-DAC replaced with 20bit-DAC.

Timing card firmware upgraded in place

New models [h1iopiscex, h1calex, h1pemex]

All models running RCG-5.5.2

h1iscey

Timing card firmware upgraded in place

h1seiex, h1seiey

Timing card firmware upgraded in place

h1susauxex, h1susauxey

Timing card firmware upgraded in place.

All models running RCG-5.5.2 (first test of new RCG)

h1pemmx, h1pemmy

Timing card firmware upgraded in place.

LHO FMCS - Mega Cleanroom Powered On

tyler.guidry@ligo.org — Thu, 04 Dec 2025 09:29:13 -0800

Author: tyler.guidry@ligo.org

Report ID: 88355

At approx 8am the cleanroom above HAM 5/6/7 was powered on in prep for vent activities and initial cleanings. As to be expected, zone 4g temp has spiked. No action on behalf of FAC is required at this time. T. Guidry K. Stewart N. Sanchez

H1 CDS - IO Chassis Timing Card Firmware Versions

david.barker@ligo.org — Thu, 04 Dec 2025 08:54:03 -0800

Author: david.barker@ligo.org

Report ID: 88354

On Tuesday 02dec2025 Marc upgraded the firmware version of the IO Chassis timing cards at both end stations and mid stations. This upgrade was done "in place" using a laptop connected to the JTAG port on the timing card.

The current timing card firmware versions for H1 are:

All are running 0xfe0 except the following which are running 0x635

h1omc0: upgraded some time ago during O4 to move its DUOTONE frequencies from [960/961Hz] to [1920/1921Hz]

h1susey: upgraded Mon 01dec2025 when its timing card was replaced as part of the LIGO-DAC upgrade

Upgraded by Marc Tue 02dec2025:

h1iscex
h1iscey
h1pemmx
h1pemmy
h1seiex
h1seiey
h1susauxex
h1susauxey
h1susey

H1 ISC - Comment to instructions for recovering alignment after gate valves are excercised

thomas.shaffer@ligo.org — Thu, 04 Dec 2025 08:29:54 -0800

Author: thomas.shaffer@ligo.org

Report ID: 88353

Created a wiki page for Recovering the IFO After Gate Valve Closures and added a link to that wiki in our ops Troubleshooting the IFO wiki. This way we can make changes next time we exercise this procedure and hopefully it leaves more bread crumbs to find it again.

OpsInfo

H1 CDS - h1iscex 20bit-DAC replacement

david.barker@ligo.org — Thu, 04 Dec 2025 08:22:56 -0800

Author: david.barker@ligo.org

Report ID: 88352

Jonathan, Jeff, Tony, Dave:

Following the upgrade of h1iscex 18bit-DAC upgrade to a 20bit-DAC Tuesday 02dec2025 we discovered the 20bit-DAC was not outputting any voltage.

Wed 03dec2025 Tony and I went to h1iscex to replace the suspect 20bit-DAC with the second DAC which was removed from the h1susex upgrade Tue02dec2025.

All while H1 was locked, we powered down h1iscex and its IO Chassis, pulled the chassis from the rack, took its lid off, replaced the 20bit-DAC and powered the chassis up while it was open.

I powered up the computer and auto started the models. H1 lost lock soon after the IOP model started running (possible Dolphin IPC minor break in transmission?).

We verified that the replacement 20bit-DAC was working, looking at both the DAC_chan7->ADC_chan30 DUOTONE inteface card loop back and h1calex drive of DAC_chan6.

We closed the chassis and pushed it back into place.

Suspect broken 20bit-DAC (removed)	190219-10
Replacement 20bit-DAC (installed)	150311-01 (S1700286)

Note that both of these 20bit-DACs came out of h1susex during its upgrade to LIGO-DACs Tue02dec2025. I'm not sure which one was driving the PI signals, and initially I chose the 2019 card for h1iscex over the older 2015 card.

Also note that the 2015 card has a LIGO S-number tag, the first I've seen on a GenStd IO card.

LHO General - Thurs DAY Ops Transition

corey.gray@ligo.org — Thu, 04 Dec 2025 07:43:47 -0800

Author: corey.gray@ligo.org

Report ID: 88351

TITLE: 12/04 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
OUTGOING OPERATOR: None
CURRENT ENVIRONMENT:
SEI_ENV state: CALM
Wind: 3mph Gusts, 1mph 3min avg
Primary useism: 0.02 μm/s
Secondary useism: 0.33 μm/s
QUICK SUMMARY:

H1 has been locked almost 15hrs....but H1 is going DOWN in prep for the HAM7 vent and will be set to IDLE.

There will be more CDS (have heard Beckhoff) work, but no "proof of life" for H1 after that work will be done.

Now the focus is on prep to vent with Kim & Nellie commencing shortly with thorough technical cleaning of HAM chambers. Other possible items on the list for today:

Turn on Kobelco purge
Forklifting furniture
HAM7 vent prep
Prep for HAM7 -Y door removal

H1 ISC - instructions for recovering alignment after gate valves are excercised

sheila.dwyer@ligo.org — Wed, 03 Dec 2025 23:01:39 -0800

Author: sheila.dwyer@ligo.org

Report ID: 88348

It seems like it would be useful to have this recipie written in one place. After the gate valves are opened and closed, we often have a hard time relocking because of alignment.

Here's what we think we should do to recover after gate valves open.

Do initial alignment without using green cameras in the loop, as the cameras are right next to the gate valves.
1. Start by using the baffle PD dither alignment script to set the TMS alignment: use the suspension guardians to misalign both ITMs and ETMs, run dither align script for both TMSs found on the INIT ALIGN MEDM, (dither align scripts, TMSX and TMSY, can run at the same time). Open the ITM baffle PD scope and watch the script find the pointing of TMS that sets the beam to PD1, PD4, and finally centered on the optic. When this finishes sucsesfully for both TMSs, there should be a dim green beam visible on both ALS cameras, if there is not check the alignment of PR3 (affects both arms) and the BS (only moves the Y arm beam). This TMS alignment has to be set before you can move onto the next step, otherwise the ITM alignment won't be right.
2. Use the suspension guardians to align both ITMs, but leave the ETMs misaligned. Run the dither alignment script for ITMX and ITMY, this time watching the ETM baffle PD scope to watch the script's progress. Once this is finished, the ITMs should be set, and we should not move them based on the cameras.
3. Use the suspension guardians to set the ETMs to aligned, and you will hopefully see mulitple beams or cavity flashes on the ALS cameras. You can manually align the ETMs to increase the flashes until they are good enough to lock the arm. Use the ALS guardians (in auto mode might be helpful) to set them to ETM_TMS_WFS_OFFLOADED, this will not run the green camera servos, it runs green WFS to the ETM and TMS alignment only to increase build up. Don't run INITIAL_ALIGNMENT or INITIAL_ALIGNMENT offloaded.
4. Align the vertex to these ITMs: set the ALIGN_IFO guardian to manual, init it to control the suspension guardians. Choose INPUT_ALIGN_OFFLOADED, once that finishes PRC_ALIGN_OFFLOADED, then MICH_BRIGHT_OFFLOADED, then SRC_ALIGN_OFFLOADED.
Make two guardian changes before you start locking the full IFO
1. Don't use the SRC1 + SRC2 ASC loops in DRMI, these don't seem to work until the alignment is set well for full lock. You can turn these off by going to lscparams, and searching for use_DRMI_ASC, setting SRC1+ SRC2 to false. Load ISC_DRMI for this change to take effect.
2. Don't shutter the ALS beams once they are no longer used for locking. In ISC_LOCK, find the edge ('IDLE_ALS', 'CARM_OFFSET_REDUCTION', 5), and reduce the weight which is normally 5 to 1, so that this path which avoids shuttering the ALS becomes the default path. Load ISC_LOCK for this change to take effect.
Start to relock as usual, going through PRMI. Stop at CHECK_DRMI_ASC, where all the DRMI ASC loops will be running other than SRC1+SRC2, and manually adjust SRM sliders to reduce POP90 and increase POP18.
You can try to lock all the way to ENGAGE_ASC for full IFO, but this may not work. If it does not, you may need to manually align DHARD, CHARD, and SRM.
1. If you are adjsuting alignments by hand, you want to keep the green beams locked to the arms as the alignment changes. To get the green alignment to follow any changes you make, stop at IDLE_ALS and turn on the scripts that servo the green TMS QPD offsets based on the green WFS. You can access this script by going to either ALS end station overview and clicking the button that says QPD OFFSETs, then using the pink drop down button to start the servo for each arm, and open the ndscope that lets you watch the progress of these servos (screenshot)
2. If the power in the two arms is mismatched (visible on the PRMI SB4 min ndscope on the front wall), this could be a sign that DHARD is misaligned.
  1. If you notice this in a state before DHARD WFS are closed, RF_DARM or CARM_OFFSET reduction , you can use the move_arm_dev script to step DHARD pitch and yaw to bring the arms closer to each other. userapps/asc/h1/scripts/move_arm_dev.py DH P 0.01, or similar.
  2. If you notice the arm powers diverging from each other after DHARD WFS are closed, this might be fixed by moving SRM while watching to make sure POP 90 stays low.
3. If the power recycling gain is low, you may need to adjust CHARD. You can step through CARM_OFFSET reduction or stop after it finishes and use 62110 to check if the refl power is too low for the arm transmission that you are at, and try to move CHARD while trying to increase the refl power (watch build_up_slow ndscope linked from the ISC guardians overview and other places).
Once you are all the way locked (congratulations), stop at PREP_ASC_FOR_FULL_IFO before you try turning on ASC. It may be a good idea to note the green QPD offsets with a screenshot, if you loose lock they wil be reverted with SDF revert but you would need to reset them to these values to relock. Also look at the ITM green camera offsets, from each ALS end station overview in the green WFS section there is a button that says CAM ITM YAW or PIT, you can take a screenshot of this screen for both ITM cameras and compare the current location of the beam centroid to the setting (screenshot)
Use a guardian shell (guardian -i ISC_LOCK) to copy and paste lines from ENGAGE_ASC_FOR_FULL_IFO manually, skipping SRC1 +SRC2. (you might grab another screenshot of the green QPDs and cameras at this point)
Then you can manual the guardian to TMS_SERVO, engage_soft_loops, and DARM offset, and take another green QPD offset + camera screenshot.
Having the DARM offset on as well as the soft loops seems to help the SRC ASC work, so try engaging those once those steps are done. (Congratulations on getting all the ASC controlled)
Important step: reset the green references. In the past we have reset the green QPD offsets by accepting them in SDF as well as the camera offsets, but it doesn't make sense to be changing the QPD offsets as they shouldn't be impacted by the gate valve moving the camera. Today once we had all the ASC engaged, we stepped the QPD offsets back to their original settings from SDF, watching the arm transmissions in the ndscope. The arm transmissions seemed fine with the original QPD offsets, so we left those there and only updated the green camera offsets. I think this should be the way we do things in the future, not reseting the QPD offsets by default.
undo the gaurdian changes from step 2 above. After the next lockloss, run initial alignment as usual, letting the green cameras be used to point the ITMs. DRMI ASC should work now that the alignment has been set.

Images attached to this report

H1 SQZ - Touched SQZR Settings & Sliders

anthony.sanchez@ligo.org — Wed, 03 Dec 2025 18:22:56 -0800

Author: anthony.sanchez@ligo.org

Report ID: 88347

TITLE: 12/04 Eve Shift: 0030-0600 UTC (1630-2200 PST), all times posted in UTC
STATE of H1: Planned Engineering & LOCKED
CURRENT ENVIRONMENT:
SEI_ENV state: CALM
Wind: 10mph Gusts, 6mph 3min avg
Primary useism: 0.02 μm/s
Secondary useism: 0.28 μm/s
QUICK SUMMARY:

SQZ_OPO_LR was giving us this error: 
"CLF frequency out of range, check CLF CMB".
I do not recall how this was resolved by Daniel while he was checking out the CMB. 

Once that was resolved we got the classic: "pump fiber rej power in ham7 high, nominal 35e-3, align fiber pol on sqzt0."  issue.
The Quarter & Half wave plates on SQZT0 were touched up to minimize H1:SQZ-SHG-FIBR_REJECTED_DC_POWER_MON. 
OPO was locked. Great!

Then the FC wasn't locking:
So FC2 was moved from its nominal location. only after I accidentally moved ZM1 and reverted it.
Fumbled with the FC2 sliders for a while, then used the clear history button.
Fumbled around some more with the FC2 sliders.
Locked the the FC with FC2 P @ 246.1 Y @ 51.1

And now the SQZ has been SQuoZe.

Forcast for tonight's wind looks good for a stable lock.

H1 ISC - Locking Summary

elenna.capote@ligo.org — Wed, 03 Dec 2025 16:58:14 -0800

Author: elenna.capote@ligo.org

Report ID: 88346

[Sheila, Jeff, Elenna, Corey]

Today we relocked with some issues. We think that the soft close of the gate valves shook the ITM green cameras enough that the green references were no longer good, which caused many alignment problems through carm offset reduction.

The SRC ASC is OFF in DRMI ASC at this time, by having the use_DRMI_ASC['SRC1'/'SRC2'] flag set to False. When locking, SRM and SR2 might need to be moved by hand before offloading DRMI ASC.

Sheila will write a more detailed alog about the process of updating the green references, because we think we have a better method now. For the summary, we have updated the green camera references, SDFed them in safe, and run an initial alignment after the lockloss.

Other guardian changes:

DARM OFFSET now occurs after DRMI TO POP and befor PREP ASC FOR FULL IFO. This is how it used to be before the OFI problems. We had some problems with SRC1 P during full IFO engagement, but the problems seemed to go away as soon as we went through DARM OFFSET
CLOSE BEAM DIVERTERS is now out of the ladder. While we troubleshoot, we want these open, and to avoid lockloss they are closed at 2 W. I removed them from the ladder completely for now.

Tony, Oli and I have been watching violin mode damping. So far, there doesn't seem to be any problems.

By eye, Jeff and I think the PCAL X crosses do not match the line height in CAL DELTA L, so there may be some calibration mismatch. I will run a cal measurement when we are thermalized.

Squeezer is not working, Daniel and others are trying to troubleshoot now.

CAL, GRD, SUS

LHO General - Wed DAY Ops Summary

corey.gray@ligo.org — Wed, 03 Dec 2025 16:29:56 -0800

Author: corey.gray@ligo.org

Report ID: 88330

TITLE: 12/03 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY:

Main goal for today was to continue to see troubleshoot H1 to see if it survived the CDS work from earlier this week (by trying to get H1 back to NLN)---Elenna and Sheila worked on this. There continued to be issues with ASC SRC---Elenna said this is common for H1 recoveries. Sheila also mentioned that the alignment issue most likely is a result of Gate Valve closures affecting the Green Camera alignment.

Recovery work above had to wait until about 11amPDT due to remaining LVEA crane inspections.

During Recovery work 20-bit DAC card was swapped out for one which was installed yesterday that had issues.
LOG:

1532-1605 Initial Alignment
1541 Crane inspection begins in South Bay [randy & CraneTech contractor]----> done in LVEA
- After lunch will do Staging and then FCES
1606-1613 Restart all of the models on h1iscex (this is for the the issue with the PCal for EX). [dave]
1640-1730 EY, EX trips to check on Dustmon Pumps (tj)
1659-1706 lvea walkthru (richard)
1707-1714 meet w/ crane inspector (tyler)
1729-1901 Moving magnetometer around HAM1 (rene, alicia)
1740-1755 Swapping in new Corner Station Dust Monitor pump & then checking flow (tj)
1756-1808 Testing out new dust monitors in the diode room (ryanC)
1803-1854 Power supply measurements at EX related to PCal & new DAC (tony)
1819-1840 Looking for picomotor mount assys in optics lab (jennie)
1839-1852 Parts hunt in West Bay (mitch)
1852-1857 LVEA walkthru (sheila)
1850 Restart locking H1
- darm to rf -> idle als -> dhard wfs
- Thought is GV soft closes affect green camera alignment so this causes recovery grief.
1941-2111 LVEA Tour for Michael Turner (cosmologist) & Dennis Overbye (NYT reporter) which was in CR and now moves to LVEA (mike, jenne)
- 2127-2156 Driving to EY
- 2206-2218 Drive to Overpass & then Back to LExC
2040-2139 Gantry crane inspections at Mechanical Room & FCES. This COMPLETES crane inspection. (randy, cranetech)
2140-2348 OPO testing + laser Hazard in the optics lab (KarMeng)
2145-2157 magnetometer tests in CER (alicia,rene)
2158 CHETA table work in the CHETA/JAC Lab (matt)
2200-2207 Hi-Bay trip (ibrahim)
2230-2308 h1iscex being shut down for the to investigate issues with 20-bit DAC (dave, tony)
2250 JAC table work in CHETA/JAC Lab (jennie)
- 2342 Looking for JAC parts in the LVEA (while we are locking H1). [jennie]
2310 Initial Alignment #2 of the day (post EX 20bit DAC swap)

H1 CAL - Comment to Tuesday Maintenance Day PCAL Impact Notes.

anthony.sanchez@ligo.org — Wed, 03 Dec 2025 15:32:33 -0800

Author: anthony.sanchez@ligo.org

Report ID: 88345

Relvent Alog: https://alog.ligo-wa.caltech.edu/aLOG/index.php?callRep=88333

Dave and I went back down to EX and Swapped out a DAC in H1ISCEX, and the Excitations and Duotone started to work again.
DAC card that was put in on Tuesday : SN 190219-10 <- bad DAC
DAC card that was swapped in today : SN150311-01 This is the working DAC.

I have since put back the OFSPD offset and Gain back to their nominal settings listed above.

CAL, CDS

H1 CDS - Comment to Upgrade h1susex to all LIGO-DACs

filiberto.clara@ligo.org — Wed, 03 Dec 2025 11:30:34 -0800

Author: filiberto.clara@ligo.org

Report ID: 88343

The following AI Chassis were modified for installation of the LIGO 32 CH DAC:

AI Chassis D1000305 S1104367 (SUSEY-C1, slot U32, new assembly drawing D2500353)
AI Chassis D1000305 S1001202 (SUSEY-C1, slot U31, new assembly drawing D2500353)
AI Chassis D1500177 S1500299 (SUSEY-C1, slot U26, new assembly drawing D2500400)

The rear panel and DAC AI Interface Board D1000551 were removed. A new D2400308 LIGO DAC Anti Image Chassis Rear Panel and LIGO DAC AI Interface D2500097 were installed.

H1 CAL - ISC EX 18-bit DAC Upgrade :: CAL Model Prep/Impact

jeffrey.kissel@ligo.org — Wed, 03 Dec 2025 10:51:10 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88341

J. Kissel, D. Sigg, D. Barker ECR E2100485 WP 12901 Continuing on the deprecation of 18-bit DAC path (ECR E2100485), we upgraded the h1iscex's DAC0 card yesterday from an 18- to a 20-bit DAC (LHO:88333). One of the front-end models that use that DAC is the h1calex model. In this aLOG, I discuss the front-end model changes we implemented to support this change. I show the differences in before vs. after in the following screenshots. All changes were made at the top level of the model, no library parts were changed. - Top level model BEFORE vs. AFTER. Functional Changes: :: Changed the CDS part representation of the DAC from a 18- to 20-bit DAC. :: Added a constant of 4.0 ***, whose output is piped into a goto tag, CAL_FACTOR. :: The CAL_FACTOR from tag is first piped into a EPICs read back for display on MEDM (and for recording in frames), which will manifest as the channel H1:CAL-EX_DAC_CAL_FACTOR :: Then CAL_FACTOR is piped into multiplication blocks downstream of the DAC outputs such that the two channels used by the model CH5 and CH6 (with the count starting at 0; CH6 and CH7 in the analog world where counting starts at 1) Aesthetic Changes: :: Added the modern labels for direct IO chassis and inter-(computer)-process communication :: Detached the RFM IPC that ships the PCAL excitations to the corner station from its direct wire pick-off and "changed" it's input to be the tag that already exists to ship the signal to the DAC :: Moved that IPC system down to the left under the "new" RFM section, which allows for the model to conform to modern convention of having clear/clean separate sections for "input" "controls" and "output." :: Changed the color of the CDS parameters block to be orange, as is standard. - Another view of the top level to better highlight which signals are multiplied by four, and where in the signal change BEFORE vs. AFTER The h1calex model has been committed, and rev-updated to to /opt/rtcds/userapps/release/cal/h1/models/ h1calex.mdl r23189 --> r34056 *** Because this model houses both the PCAL system, Hardware Injection and the DuoTone system -- critical flywheels for the detector calibration, we decided to implement our usual gain scaling of (exactly) 4.0x to compensate for the change in calibration (from 20/2^18 to 20/2^20 [ Vpp_differential / ct]) the DAC card upgrade as a hard-coded constant in the front-end, rather than in an "adjustable/changeable" filter module in a filter bank just upstream of the DAC output.CAL, CDS, DetChar, ISC

Images attached to this report

LHO VE - Wed CP1 Fill

david.barker@ligo.org — Wed, 03 Dec 2025 10:28:38 -0800

Author: david.barker@ligo.org

Report ID: 88342

Wed Dec 03 10:09:57 2025 INFO: Fill completed in 9min 54secs

Gerardo confirmed a good fill curbside. Plot looks strange because temps were starting positive.

Images attached to this report

H1 CDS - Comment to Upgrade h1iscex 18bit-DAC to 20bit-DAC

jeffrey.kissel@ligo.org — Wed, 03 Dec 2025 10:09:58 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88340

Tagging CAL and PEM because this is "their" DAC. We've done the typically thing with a DAC upgrade: - the DC calibration of the DAC has changed from (roughly) 20 / 2^18 [Vpp_differential / ct] to (roughly) 20 / 2^20 [Vpp_differential / ct] - Such that upstream control systems "don't have to be retuned" we apply a digital factor of (exactly) 4.0x to all output signals for each DAC channel As such, for example, the calibration of the PCAL actuation / excitation chain is likely now slightly different, and should be remeasured.CAL, PEM

H1 CDS - Comment to Upgrade h1iscex 18bit-DAC to 20bit-DAC

david.barker@ligo.org — Wed, 03 Dec 2025 10:01:54 -0800

Author: david.barker@ligo.org

Report ID: 88339

Model changes:

h1iopiscex (Dave) updated to new DAC configuration

h1calex, h1pemex (Jeff, Oli) updated to new DAC configuration

All models on this front end, including h1iscex and h1alsex, were built and installed with RCG-5.5.2

H1 CDS - Comment to Upgrade h1susex to all LIGO-DACs

david.barker@ligo.org — Wed, 03 Dec 2025 10:00:11 -0800

Author: david.barker@ligo.org

Report ID: 88338

Model Changes:

h1iopsusex (Dave) modified to new DAC configuration. SWWD section updated to new DAC cards

h1susetmx, h1sustmsx, h1susetmxpi (Jeff, Oli) updated to new DAC configuraiton.

All models built and installed with RCG5.5.2

H1 CDS - Comment to Upgrade h1susex to all LIGO-DACs

jeffrey.kissel@ligo.org — Wed, 03 Dec 2025 09:58:10 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88337

Tagging SUS and CAL, as these are the DAC cards for SUS ETMX. We have done the logical thing of applying a gain factor of 1024x in the COIL and ESDOUTF banks to again mimic the calibration function of a 18- bit, like the factor of 4x that's been in play for a while after we upgraded to a 20-bit DAC. But, of course at the calibration group's level of precision / accuracy the DAC cards / and channels within will NOT have the same calibration as 2^18 / 20 [ct/Vpp_differential] * 2^10 = 2^28/20 [ct/Vpp]. This will change the open loop gain magnitude of the top mass damping loops, but to a much less important degree. I expect a similar level of impact on ISC loops wrapped around ETMX too. Also now that these LIGO 32CH DAC have had their maximum output voltage tuned to spit out 10.0 Vpp differential at the output of the AI chassis. This is unlike the 18-bit DAC who's output saturated at ~9.7 Vpp, or the 20-bit DACs who's output saturated at ~9.3Vpp.CAL, SUS

H1 CDS - Upgrade h1susex to all LIGO-DACs

david.barker@ligo.org — Wed, 03 Dec 2025 09:57:36 -0800

Author: david.barker@ligo.org

Report ID: 88336

WP12901 Daniel, Marc, Fil, Jonathan, Richard, Jeff, Oli, EJ, Dave:

Following from Monday's success in upgrading h1susey to the new LIGO-DACs on Tuesday 02dec2025 we upgraded h1susex to use LIGO-DACs.

This was a slightly different upgrade compared to h1susey because for the past 18 months h1susex ESDs have been driven using an early version of the LIGO-DAC. The h1susetmx model was using the GenStd 18/20-bit DACs for the upper stages and the LIGO-DAC for the L3 and ESD. The other models (h1sustmsx and h1susetmxpi) continued to use the Gen Std DACs.

The ESD and PI drives were being driven by a single 20bit-DAC using the special PI-AI chassis (first 6 chans through standard filters and output via DB15, last 2 chans through PI filters and output via DB9). When we upgraded the ESD drives to the LIGO-DAC we retained the original PI-AI chassis for these signals and temporarily installed the spare PI-AI chassis for h1susetmxpi 20bit-DAC's exclusive use.

The original LIGO-DAC used the 8-channel interface card. This card took the 32 channels from the LIGO-DAC and outputed the first 8 using its onboard DB25 connector. The remaining 24 channels were distributed using 3 Header Slot Plates (each with a DB25) ribbon cabled to the interface card. To fit these into the chassis, we displaced the two BIO cards to A4-3 and A4-4.

The IO Chassis changes were then:

Remove first-gen LIGO-DAC card, its 8chan interface card and the 3 header slot plates.

Remove the 3 18bit-DACs and their interface cards

Remove the 2 20-bit DACs and their interface cards

Install 2 LIGO-DACs in A1-4 and A2-2 with their new LIGO-DAC interface cards

Move the 2 BIO cards back to A4-1 and A4-2.

Fil upgraded all the AI chassis for LIGO-DAC SCSI Connection, duplicating what was done at EY. The second LIGO-DAC drives the PI-AI chassis, the first LIGO-DAC drives the 2 standard AI chassis, now daisy chained together.

Temporary cabling from the original LIGO-DAC chans 16-31 looped over to h1iscex were removed.

LIGO-DACs ADDED

DAC0 S2500451	Interface card SN007
DAC1 S2500456	Interface card SN005

Cards Removed

First Gen LIGO-DAC	S2400042
LIGO-DAC Interface Card	"2" in marker pen
18bit-DAC	110425-32
18bit-DAC	110425-22
18bit-DAC	101208-74
20bit-DAC	190219-10*
20bit-DAC	150311-01 (S1700286)
18/20-DAC Interface card	S1200225
18/20-DAC Interface card	S1104340
18/20-DAC Interface card	S1201759
18/20-DAC Interface card	S1102690
18/20-DAC Interface card	S1102687

* 20bit-DAC installed into h1iscex, now suspect.

H1 CDS - Comment to Upgrade h1iscex 18bit-DAC to 20bit-DAC

david.barker@ligo.org — Wed, 03 Dec 2025 09:30:44 -0800

Author: david.barker@ligo.org

Report ID: 88335

DCC docs for "18bit AI Chassis"

D1101785 [front section]

D1200316 [whole chassis]

The "AI WD" green LED on the rear panel is ON when the serial cable from the DAC Interface cable is connected and OFF when the cable is disconnected, suggesting the DAC is driving the WD line correctly at least.

H1 CDS - Upgrade h1iscex 18bit-DAC to 20bit-DAC

david.barker@ligo.org — Wed, 03 Dec 2025 08:48:58 -0800

Author: david.barker@ligo.org

Report ID: 88333

WP12901. Daniel, Jeff, Oli, Fil, Marc, Jonathan, EJ, Tony, Dave:

Summary:

Yesterday I replaced h1iscex's 18bit-DAC with a 20bit-DAC as part of the project to eliminate all 18bit-DACs from production. There is currently no indication that the 20bit-DAC is driving the AI chassis with any voltage, investigation is ongoing.

Details:

The 18/20 bit DACs use the same interface card, so for the upgrade I was able to pull the IO Chassis out half way with cables still attached to access the PCIe bus. I removed the old 18bit-DAC and replaced it with on of the 20bit-DACs from h1susex upgrade

old 18bit-DAC (removed)	110425-03
new 20bit-DAC (installed)	190219-10

I do not know if the 20bit-DAC from h1susex was the one driving the PI or the one which had been idle since the LIGO-DAC went in mid 2024.

The original interface card and ribbon cable were reused. No field cabling was disconnected, no AI chassis were powered down.

Upgrade was done between 12:00 and 13:00 Tue 02dec2025.

Later that afternoon Tony found that the PCAL readbacks were not responsive. Tony and I went to EX around 17:00 to verify the 20bit-DAC was installed and connected correctly, it was.

This DAC has a special AI Chassis, D1101785 "aLIGO 18 Bit AI Chassis" which has handy BNC pickoffs for all 8 channels. We put a scope on the two channels being driven by h1calex (6,7) and could see no signal.

Also the last channel on the AI is loop-backed to the first ADC AA chassis with a DB9 cable, and the IOP is configured by SDF to drive the duotone from DAC0-chan7 back to ADC0-chan30. No signal is seen there either since the upgrade.

LHO VE - Tue CP1 Fill

david.barker@ligo.org — Wed, 03 Dec 2025 08:20:54 -0800

Author: david.barker@ligo.org

Report ID: 88332

Tue Dec 02 10:01:28 2025 INFO: Fill completed in 1min 27secs

Does not look like a good fill. Will try again tomorrow

Images attached to this report

LHO General - Comment to Wed DAY Ops Transition

corey.gray@ligo.org — Wed, 03 Dec 2025 08:05:38 -0800

Author: corey.gray@ligo.org

Report ID: 88331

Got word there are issues for PCal at EX (after investigations by Tony & Dave last night).

After the alignment is done, Dave is going to restart models on h1iscex & then after that they will possibly swap back in the 18-bit DAC (after the 20bit DAC was installed yesterday).

CDS

LHO General - Wed DAY Ops Transition

corey.gray@ligo.org — Wed, 03 Dec 2025 07:45:51 -0800

Author: corey.gray@ligo.org

Report ID: 88329

TITLE: 12/03 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
OUTGOING OPERATOR: None
CURRENT ENVIRONMENT:
SEI_ENV state: CALM
Wind: 5mph Gusts, 3mph 3min avg
Primary useism: 0.02 μm/s
Secondary useism: 0.27 μm/s
QUICK SUMMARY:

H1 was IDLE overnight (had troubles getting through DRMI and a few steps beyond yesterday afternoon/eve---see Oli's log). In the middle of an Initial Alignment. Then we'll see about locking...

Day #2 of Crane Inspection work continues: This morning will be work for the South Bay crane, but will also need pendant work; this should go until about noon. (Then remaining cranes would be: Filter Cavity End Station, Staging Bldg, and some gantry cranes.) Yesterday, rest of LVEA cranes were inspected as well as End & Mid Stations.

(it's been almost 15min and Green Arms are almost aligned from Initial Alignment.)

H1 CAL - Comment to Tuesday Maintenance Day PCAL Impact Notes. UPDATE

anthony.sanchez@ligo.org — Tue, 02 Dec 2025 17:42:44 -0800

Author: anthony.sanchez@ligo.org

Report ID: 88328

I was not able to get PCALX excitations in DARM. The new 20 bit H1IOPSCEX DAC is then plugged into an 18 bit AI chassis. Dave and I went out to the End station and put an Oscilloscope on it to try and see any sort of excitation coming out of the 18 Bit AI chassis. No dice.
We will need to do more troubleshooting tomorrow.

CAL, CDS

Images attached to this report

H1 General - IFO in IDLE for the night

oli.patane@ligo.org — Tue, 02 Dec 2025 17:40:34 -0800

Author: oli.patane@ligo.org

Report ID: 88327

The IFO has been trying to relock for a bit now, but we were having multiple locklosses, from DHARD_WFSx3, BS_STAGE2, and CARM_OFFSET_REDUCTION. Most of the locklosses looked sudden (based on quick look at buildups ndscope), but the last attempt, we started getting SRM saturations and the PR gain was moving all over the place. I remembered that Jenne and RyanS had been saying that SRC1 wasn't being cooperative yesterday (88298), so I turned off the SRC1 and SRC2 loops and that stopped the oscillation. Unfortunately, we lost lock soon after in DHARD_WFS. I was (am) about to go home so I've put the detector in IDLE for the night.

ISC

Images attached to this report

H1 PEM - Added DAC calibration filters for PEM EX

oli.patane@ligo.org — Tue, 02 Dec 2025 17:26:37 -0800

Author: oli.patane@ligo.org

Report ID: 88320

h1pemex was upgraded from an 18-bit to a 20-bit DAC today, so we needed to make sure we had a calibration correction. The new filter banks that Jeff had put in (88321) for the calibration correction are called H1:PEMEX_EX_DACOUTF_1, H1:PEMEX_EX_DACOUTF_2, H1:PEMEX_EX_DACOUTF_3, and H1:PEMEX_EX_DACOUTF_4. I installed a filter called 20BitDAC that was a gain(4) in FM10 of each of these filter banks, loaded them in, and turned them on along with the input/output/gain of the filter banks. I've accepted these changes in sdf safe

CDS

H1 SUS - SATMON medm screen updated for 28-bit DACs for ETMX, TMSX

oli.patane@ligo.org — Tue, 02 Dec 2025 17:16:24 -0800

Author: oli.patane@ligo.org

Report ID: 88326

Similar to what Ryan C did (88311), I've updated the saturation threshold values for ETMX M0/L1/L2/L3 and TMSX M1 stages to align with the new 28-bit DACs. Changes have been comitted to svn as r34061

H1 PEM - New end station dust monitor pumps running overnight

thomas.shaffer@ligo.org — Tue, 02 Dec 2025 16:58:45 -0800

Author: thomas.shaffer@ligo.org

Report ID: 88325

I've installed a Welch WOB-L 2546B-01 at each end station to replace the Gast 523 pumps that we have been using. I've set the pressure to -19inHg and checked the flow at the dust monitor on the floor was 2.8L/min. The new pumps are much quieter, ~84dB vs ~67dB, but at a lower frequency. I'll post more photos of the setup and more details tomorrow after we see how they run over night.

H1 General - Some Beckhoff SDF Channels Restored

ryan.short@ligo.org — Tue, 02 Dec 2025 16:44:21 -0800

Author: ryan.short@ligo.org

Report ID: 88323

Following the Beckhoff updates today (see alog88317), several settings needed to be restored in CS_ISC, EX_AUX, and EY_AUX after the initial SDF wrangling that was done after all the upgrades were finished.

As a reminder (for myself and others), when a Beckhoff computer is restarted, its settings are brought back up according to an internal settings file on that computer, NOT according to the safe.snap SDF table, unlike a traditional frontend model. This means the SDF tables for the restarted Beckhoff computers (basically anything with SYS in the name) will show several differences, that in most cases should be REVERTED. It's also useful to check the not monitored channels for differences, as we found a few of those today, although they were mostly just picomotor settings. See attached screenshots.

CDS, ISC, OpsInfo

Images attached to this report

LHO General - Tues DAY Ops Summary

corey.gray@ligo.org — Tue, 02 Dec 2025 16:42:43 -0800

Author: corey.gray@ligo.org

Report ID: 88301

TITLE: 12/02 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY:

Main activity of the day was the the SUS DAC swap at EX (with the addition of more CDS work at both end stations as well).

In parallel, there was also crane inspection work which initiated gate valve closures due to loads needing to be craned over the beam tubes in the LVEA. Then in the afternoon, it was decided to open the gate valves for locking (so we could see how the End Stations looked after their big changes today).

[Through today's recovery to relocking, there were several items which needed to be done. Had much help from many who made recovery fairly easy **knock on wood**.]

Towards the end of the shift, able to see light flashing in the arms, and started an Initial Alignment (one gotcha was during Scan Alignment of Green Arm alignment which made the ALSx + y guardian nodes red---Ryan and Oli were on top of it and able to get alignment back. Other than that, alignment completed with no other issues. Moved on to locking and locked DRMI pretty fast on the first attempt....unfortunately there was a lockloss at DHARD_WFS.

NOTES:

Not totally sure of where we want to leave H1 for the night. There may be other people on-site to babysit for a bit (currently, I'm leaving H1 as it is trying to lock (had DRMI lockloss for a 2nd time post today's big day). Ryan & Oli happen to be here to babysit, but if H1 isn't locked after the last operator leaves, ISC_LOCK should be taken to DOWN!
DIAG MAIN has the following note: "HWS: HWS code stopped for ITMy"
VIOLIN_DAMPING is also in PAUSE (as was the case yesterday)
PCal also having issues, but Tony is looking at that with Dave

LOG:

1556-1711 EX (kim) & EY (nellie) & then both at FCES technical cleaning
- 1730-1858 lvea clean (nellie.kim)
1610 lvea wifi turned on...since no more observing, keeping ON + turned on mid stations
1610 Crane inspection crew begins (will wait on Gate Valves) (randy, tyler)
- In the afternoon, started moving down the X-arm & Y-arm (randy, tyler)
- 2359 Back at Corner (done?)
1610 LVEA GateValves closed: GV5, GV7, FC-GV (jordan, travis)
- 1625 AIP & pressure alarm handler alarms
1614-1800 Norco LN2 truck#1 to MX cp6
1616 EX SUS DAC swap begins (jeff, dave, fil, jonathan)
- EX hardware work completed
1700-1822 Pest control (chris)
1704-1801 Exit sign install near CER (eric)
1732-1742 PCal sphere swap (tony)
1749-1831 firmware timing at EX (marc, jonathan)
1749-1800 refcav alignment touch-up (jason)
1750 testing opo (KarMeng)
- 1755-1804Looking for power supplies in lvea (kar meng.sheila)
1751-1759 moving jac stuff in optics lab (jennie.betsy)
1757-1835 checking on crane crew & 3ifo checks (tyler)
1758-0007 ey purge air test/check (jordan, gerardo)
- 2317 Ending purge air test (jordan, travis)
1822-2001 Norco LN2 truck#1 to EX cp8
1829-1951 dustmon pump tests (tj)
- 2106-2130 Cont after lunch & then a meeting (tj)
- 2236-2325 Back to EY to finish (tj)
- 2327-0026 EX to turn on new dustmon pump (tj)
1850-1935 firmware timing at EY (marc, jonathan)
1935-2017 Firmare timing at MX, MY (marc, jonathan)
1945 Verbal reminder for sweeping lvea!
1949: Got word from Tyler gate valves can open (heavy loads over beam tubes complete, but still doing other work and want to see if if it's worth it to keep them closed a bit longer)
2006-2037 LVEA walkthru (betsy, travis)
2121-2044 crane assistance in lvea (tyler)
2132 Beckhoff work (daniel)
2155-2335 Magnetometer check in CER (alicia)
2158 OPO work cont. (Kar Meng, Eric)
- 2231 Kar Meng out & laser SAFE for Eric
- 2334 Eric out
- 2355 OPO tests continue + laser HAZARD (KarMeng.Eric)
2234 Gate Valves opening (travis, jordan, gerardo)
2236-2320 cheta enclosure work (matt)
2336 Taking photos of SUS racks (dave)
2340 Initial Alignment started
- Scan Alignment had error & need ALS restarts (oli took care of this)
2351-0028 Moving magnetometer & its cable (alicia, rene, sam)

LHO VE - GV5 and GV7 Cycled for LVEA Crane Inspections

jordan.vanosky@ligo.org — Tue, 02 Dec 2025 16:15:46 -0800

Author: jordan.vanosky@ligo.org

Report ID: 88322

GV5 and GV7 were soft closed at ~8:30am local time today to facilitate equipment craning for crane inspections. We also closed FC-GV 3&5 to isolate the FCT. They were opened at ~3pm local time at the completion of the vertex crane inspection.

Closing WP 12908

H1 PEM - ISC EX 18-bit DAC Upgrade :: PEMEX Model Prep/Impact

jeffrey.kissel@ligo.org — Tue, 02 Dec 2025 16:03:00 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88321

J. Kissel, D. Sigg, D. Barker ECR E2100485 ECR E2200401 WP 12901 Continuing on the deprecation of 18-bit DAC path (ECR E2100485), we upgraded the h1iscex's DAC0 card today from an 18- to a 20-bit DAC. One of the front-end models that use that DAC is the h1pemex model. Here's the before vs. after for the models. While there, I found and left the new ADC card from ECR E2200401's PEM sensor array expansion. I'd thought it was installed solely for characterizing the 32CH LIGO DAC, but it had only been temporarily used for that. It should be there! And also, the electric field meter ADC should also remain there. If the PEM team wants to account for the factor of 4x gain change in the DAC calibration, I installed new DACOUTF filters upstream of the GDS filters that are used to drive the DACs. The model has been committed to /opt/rtcds/userapps/release/pem/h1/models/ h1pemex.mdl : r28026 --> r34059CAL, ISC, SYS

Images attached to this report

H1 SUS - Added/Updated DAC calibration filters in COILOUTF for TMSX and ETMX for new DACs

oli.patane@ligo.org — Tue, 02 Dec 2025 15:37:47 -0800

Author: oli.patane@ligo.org

Report ID: 88319

Same as 88289, we updated the DACs for ETMX and TMSX, so we needed to update the calibration gain to account for the difference in bits. I added 28BitDAC calibration gains for ETMX M0/R0/L1/L2/L3 and TMSX M1 in COILOUTF FM10 and got rid of any lingering 20BitDAC filters. I did the same for ETMX PI. I loaded these filters in and turned them on, and accepted them as on in sdf safe

CDS

H1 CAL - Tuesday Maintenance Day PCAL Impact Notes.

anthony.sanchez@ligo.org — Tue, 02 Dec 2025 15:23:38 -0800

Author: anthony.sanchez@ligo.org

Report ID: 88318

Tuesday Maintenance day impact notes.

Due to Beckhoff upgrades and restarts the PCAL lasers were shutoff.
When Beckhoff came back up the PCAL Lasers oddly didn't come back up this time.
The H1:CAL-PCALX_LASERPOWERCONTROL voltage was set to 0. I took that back to 5V for both arms.
Turned H1:CAL-PCALX_LASERENABLE back on.
H1:CAL-PCALX_SHUTTERPOWERENABLE back on.

Arm specific Settings :

PCALX:
H1:CAL-PCALX_OPTICALFOLLOWERSERVOOFFSET was set back to 3.65V.
H1:CAL-PCALX_OPTICALFOLLOWERSERVOGAIN : 39.60 dB

PCALY:
H1:CAL-PCALY_OPTICALFOLLOWERSERVOOFFSET : 3.80 V
H1:CAL-PCALY_OPTICALFOLLOWERSERVOGAIN : 38.56 V

Hey future Tony, Today is the day the X Arm 18bit DAC was changed out for a 20bit as well.

H1 DAQ - Slow Controls Software Upgrade

daniel.sigg@ligo.org — Tue, 02 Dec 2025 15:22:27 -0800

Author: daniel.sigg@ligo.org

Report ID: 88317

We switched to the spare slow controls computer that is running Windows 10 IoT Enterprise LTSC, 21H2 (OS build 19044.4780), and the most recent TwinCAT 3.1 (4026.19.0). This TwinCAT version uses a packet manager and has changed the install directory to C:\Program Files (x86)\Beckhoff\TwinCAT. It supports Visual Studio 2022 and the new Altium workflow.

One new "feature" is that the PLC boot project needs to be activated in a separate step (previous versions would do this automatically after a build). We updated the install scripts to accommodate this.

We also tried a new TcIoc that was linked against EPICS 7, but it crashed during SDF restore repeatedly. We reverted back to the previous version linked against 3.15.9.

X1 DTS - Comment to SPI Pathfinder, Phase noise measurements for Keysight 33600A waveform generator

joshua.freed@ligo.org — Tue, 02 Dec 2025 13:57:20 -0800

Author: joshua.freed@ligo.org

Report ID: 88316

Edits to previous post. Graph: X axis label should be 'Frequency offset from 80MHz (Hz)' and y-axis label should be 'dbc'

Keyradwref.png and Keyradworef.png are the requirements for the phase noise of our oscilator with SPI having and not having a reference interferometer respectivly. In the final SPI pathfinder install, we will have a reference interferometer giving us much less stringent requirements on our oscialtors phase noise. But during the build, it may be nessisary to run tests without a reference interferometer, I plotted the without reference interferometer if that situation ever does come up.

Images attached to this report

H1 ISC - PCIe Timing Card Firmware Updated

marc.pirello@ligo.org — Tue, 02 Dec 2025 13:22:30 -0800

Author: marc.pirello@ligo.org

Report ID: 88315

Per WP12909 we updated firmware on the PCIe Timing Cards at EX, EY, MX, and MY, sticker applied to each updated chassis.

EX:
H1-SUSAUX-EX-V5 (S1103885) with timing card (S2101138) firmware updated
H1-SUS-EX-V5 (S1900326) with timing card (S2101152) firmware updated
H1-SEI-EX-V5 (S1900235) with timing card (S2101093) firmware updated
H1-ISC-EX-V5 (S1900329) with timing card (S2101158) firmware updated

EY:
H1-SUSAUX-EY-V5 (S1103621) with timing card (S2101168) firmware updated
H1-SUS-EY-V5 (S1900238) ** Timing Card Replaced Monday ** applied updated sticker to chassis.
H1-SEI-EY-V5 (S1900231) with timing card (S2101173) firmware updated
H1-ISC-EY-V5 (S1900237) with timing card (S2101109) firmware updated

MX:
H1-MX (S1105017) with timing card (S2101151) firmware updated

MY:
H1-MY (S1103622) with timing card (S2101085) fimrware updated

D. Barker, F. Clara, J. Hanks, R. McCarthy, M. Pirello, D. Sigg

ISC, SEI, SUS

H1 TCS - TCS Monthly Trends (FAMIS #38835)

corey.gray@ligo.org — Tue, 02 Dec 2025 12:46:22 -0800

Author: corey.gray@ligo.org

Report ID: 88313

Attached are monthly TCS trends for HWS & CO2 lasers. (FAMIS link)

TCS

Images attached to this report

H1 PEM - HVAC Fan Vibrometers FAMIS Check (FAMIS 27646)

corey.gray@ligo.org — Tue, 02 Dec 2025 11:51:08 -0800

Author: corey.gray@ligo.org

Report ID: 88314

For FAMIS #27646: All fan trends look nice and flat!

Images attached to this report

H1 SUS - Comment to Maybe seeing fuzziness in ETMY oplevs

jason.oberling@ligo.org — Tue, 02 Dec 2025 11:16:02 -0800

Author: jason.oberling@ligo.org

Report ID: 88312

Capturing my comments in the Mattermost chat in this alog. I think this is OpLev laser glitching. From the DetChar summary page for December 2nd around 1am UTC, clear laser glitching is seen in the SUM spectrogram (1st attachment). These glitches don't always come through in pitch and yaw, but when they do they tend to show in pitch more often than yaw. Looking at the pitch and yaw spectrograms (2nd and 3rd attachments, respectively) at the same time period shows this; clearly seen in pitch, but not so much in yaw (later on seen in both).

Images attached to this report

H1 SUS - SATMON updated for new 28bit DACs

ryan.crouch@ligo.org — Tue, 02 Dec 2025 11:04:39 -0800

Author: ryan.crouch@ligo.org

Report ID: 88311

After the DACs were upgraded at EndY alog88274, I've updated SATMON.adl for ETMY (M0, L1, L2, L3), and TMSY (M0). I had to add a new item to the legend on the bottom right for the 28bit levels.

Images attached to this report

H1 SEI - ISI CPS Noise Spectra Check Weekly FAMIS

oli.patane@ligo.org — Tue, 02 Dec 2025 10:51:23 -0800

Author: oli.patane@ligo.org

Report ID: 88307

Closes FAMIS#27537, last checked 88075
This is being compared to two weeks ago (FAMIS#27534) since it didn't run correctly last week.

Observations
- All HAMs except HAM7, and all CS BSCs ST1 - V1/V2/V3 all look a bit extra noisy between 6.5-9 Hz, but it's not the worst and I assume is probably due to local ground motion.

- Nothing else looks weird

Non-image files attached to this report

CPS_spectra_08:55-12_02_2025.pdf

H1 CAL - Turning OFF H1 PCALY 1153.2 Hz Calibration Line

jeffrey.kissel@ligo.org — Tue, 02 Dec 2025 10:14:15 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88310

J. Kissel, E. Capote, J. Betzwieser Today, I turned OFF the 1153.2 Hz PCALY Calibration Line by changing the frequency and amplitude to 0.0, and turning off the corresponding element in the OSC SUM matrix. $ caput H1:CAL-PCALY_PCALOSC9_OSC_FREQ 0.0 $ caput H1:CAL-PCALY_PCALOSC9_OSC_SINGAIN 0.0 $ caput H1:CAL-PCALY_OSC_SUM_MATRIX_1_9 0.0 I've saved those settings in the OBSERVE / safe.snap SDF files to make that stick (they're the same file, soft-linked together). Context This line has been on consistently throughout O4, at the same frequency with no change in amplitude -- but never used for any science; t'was just eating up PCAL range. And now the REST of the story... In O3, the PCAL team began prototyping a constant comparison between PCALX and PCALY in order to determine \chi_{XY} . On Sep 11 2019, we turned on a line at 1153.1 Hz at both end-stations with opposite sign forming a "canceling line" (LHO:51915). Realizing that a truly canceled line has no SNR above the DARM noise to make any statistically significant statement, they moved to 395.1 Hz for a minute (LHO:53259). Then, they finally tried separating them near the end of O3 at 1153.1 and 1153.2 Hz lines on PCALX and PCALY respectively (LHO:54876). Finding they still needed more SNR, they moved the comparison briefly down to 530.2 and 530.1 Hz (LHO:54868); this became the final measurement for P2000113), and then returned them to former frequencies of LHO:54868 on 2023-03-03 (LHO:55386)... and then we just never turned off the PCALY portion #globalpandemicwhoops. The corresponding PCALX portion, at 1153.1 Hz, was unceremoniously turned off without aLOG on a Thursday afternoon between O3 and O4, at 2022-12-08 22:29 UTC (14:29 PDT).DetChar, ISC

H1 PSL - PSL FSS RefCav Remote Beam Alignment Tweak

jason.oberling@ligo.org — Tue, 02 Dec 2025 10:00:00 -0800

Author: jason.oberling@ligo.org

Report ID: 88309

The RefCav reflected spot looked off this morning and the trends Ryan posted yesterday showed a large drop in RefCav TPD, so I tweaked the beam alignment into the RefCav from the Control Room; this was done with the ISS ON and the IMC unlocked. When I started the TPD was ~0.473 V, and when I finished the TPD is ~0.518 V. This isn't as high as we have been (~0.55 V), so this is an indication of another misalignment on the PSL table (most likely the double-pass AOM, which is our usual culprit for on-table alignment work). We're not too far down right now and we are not consistently observing, so we will continue to monitor as usual and will do an on-table alignment should the TPD continue to drop.

H1 SEI - HEPI Pump Trends Monthly FAMIS

oli.patane@ligo.org — Tue, 02 Dec 2025 09:40:18 -0800

Author: oli.patane@ligo.org

Report ID: 88308

Closes FAMIS#37211, last checked 87059

HPI-PUMP_L0_CONTROL_VOUT has been trending up for the past ~2 weeks.
All other HEPI pump trends looking as expected.

Images attached to this report

H1 SUS - h1susex DAC Upgrade: SUS ETMX / TMSX/ ETMXPI Simulink Model Prep for 28-bit 32CH DACs

jeffrey.kissel@ligo.org — Tue, 02 Dec 2025 09:25:01 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88305

J. Kissel ECRs: E2400409 and E2500296 IIET: 35739 and 35706, respectively WP: 12901 DWG: D1002741 This morning, I updated the front-end user models for the X end station -- h1susetmx, h1susetmxpi, and h1sustmsx -- leveraging all the work and gotchas from yesterday's 32CH DAC upgrade of the Y-end station front end models (Primary models LHO:88280, Inconsequentially Updating Libraries LHO:88283, and Adding DAC compensation filters to the ETM PI library part LHO:88285). The good thing about having the end-stations use identical wiring diagrams means that I can literally copy and paste the digital representations of the DAC connections and cards. I've confirmed that the library part change to the ETM PI library correctly updated in the h1susetmxpi model without effort. The only "difference" was that the top level of the ETMX QUAD model, h1susetmx, had all of the messy prototyping pick-off infrastructure for the early 32CH DAC testing which can now all be ripped out and made to look clean and simple like ETMY's. I attach before vs. after screenshots for posterity. The revisions of the models that have been successfully compiled: /opt/rtcds/userapps/release/sus/h1/models/ h1susetmx.mdl r28431 --> r34046 BEFORE vs AFTER sus/common/models/ESD_LINEARIZATION_WITH_CHARGE_MASTER.mdl : r16336 --> r30316 h1susetmxpi.mdl r27215 --> r34048 BEFORE vs AFTER sus/common/models/PI_MASTER_V2.mdl : r26600 --> r34033 h1sustmsx.mdl r27182 --> r34050 BEFORE vs AFTER And as before, I also attach a screenshot of the usage of DAC0 and DAC1 across front-end models. Today I decided to be a little more color-coded with my notes on channel usage; red for consumed/reserved in other models, orange for actually physically unused. CDS, ISC, SUS

Images attached to this report

H1 CDS - Updated leap second databases on core infrastructure

jonathan.hanks@ligo.org — Tue, 02 Dec 2025 09:20:06 -0800

Author: jonathan.hanks@ligo.org

Report ID: 88306

It was time to update the leap seconds file on some infrastructure systems, our famis task came due.

Debian 11 hasn't updated the tzdata package yet, and it expires end of this month.

I updated the leapseconds database on

h1daqdc0
h1daqfw0
h1daqnds0
h1daqtw0
h1daqgds0
h1daqdc1
h1daqfw1
h1daqnds1
h1daqtw1
h1daqgds1
h1fs0
h1fs1
h1hwinj1
h1hwsmsr
h1hwsex
h1hwsey
h1fescript0
h1guardian
h1vmboot5-5 (and its diskless root)
cdsfs0
cdsfs1
cdsfs2
cdsfs3
cdsfs4
cdsfs5
h1digivideo2

Link to the last time we did this: https://alog.ligo-wa.caltech.edu/aLOG/index.php?callRep=85270

LHO General - Comment to Tues DAY Ops Transition

david.barker@ligo.org — Tue, 02 Dec 2025 08:31:15 -0800

Author: david.barker@ligo.org

Report ID: 88304

I've bypassed some alarms:

Bypass will expire:
Tue Dec 2 02:30:20 PM PST 2025
For channel(s):
H0:VAC-LX_GV7_ZSM179A_VALVE_ANIM
H0:VAC-LY_GV5_ZSM159A_VALVE_ANIM
H1:CDS-STAT_NUMBER_OF_ERRORS
H1:DAQ-H1EDC_CHAN_NOCON

H1 CDS - Comment to h1susey upgrade to LIGO-DACs

david.barker@ligo.org — Tue, 02 Dec 2025 08:27:48 -0800

Author: david.barker@ligo.org

Report ID: 88303

h1susey card information:

Removed:

18bit-DAC	110425-26
18bit-DAC	110425-19
18bit-DAC	101208-73
20bit-DAC	200217-18*
20bit-DAC	200217-04
18/20-DAC IF	S1000869
18/20-DAC IF	S1000866
18/20-DAC IF	S1000868
18/20-DAC IF	S1104339
18/20-DAC IF	S1500234*

* left at EY for h1iscey upgrade to 20bit-DAC

LHO General - Comment to Tues DAY Ops Transition

corey.gray@ligo.org — Tue, 02 Dec 2025 07:43:05 -0800

Author: corey.gray@ligo.org

Report ID: 88302

1541: For Maintenance Day, took H1's SEI_ENV to Maintenance (from NLN/noSQZ) & this resulted in a lockloss.

LHO General - Tues DAY Ops Transition

corey.gray@ligo.org — Tue, 02 Dec 2025 07:31:51 -0800

Author: corey.gray@ligo.org

Report ID: 88300

TITLE: 12/02 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
OUTGOING OPERATOR: None
CURRENT ENVIRONMENT:
SEI_ENV state: CALM
Wind: 2mph Gusts, 1mph 3min avg
Primary useism: 0.03 μm/s
Secondary useism: 0.30 μm/s
QUICK SUMMARY:

H1's been locked 13.5+hrs with a range hovering around132Mpc and no squeezing. There was a minor optics dust alarm at around 534amPDT (cleared in 10min).

H1 ISC - Comment to Locking success after Yend DAC swaps

jenne.driggers@ligo.org — Tue, 02 Dec 2025 07:07:45 -0800

Author: jenne.driggers@ligo.org

Report ID: 88299

The IFO is still locked, but I think maintenance activities can start at any time.

H1 ISC - Locking success after Yend DAC swaps

jenne.driggers@ligo.org — Mon, 01 Dec 2025 18:02:17 -0800

Author: jenne.driggers@ligo.org

Report ID: 88298

[RyanS, Oli, Jenne, Jeff]

Locking went well, and we're currently at NomLowNoise (no squeezing though). We're good to go for swapping the Xend DACs tomorrow.

SRC1 during DRMI ASC seems to pull things away at the last little bit rather than converging, so we've been turning it off by hand. If it's still being problematic when we next try to lock (tomorrow? or Wed?), then we should set it to False in the DRMI guardian.

We also turned SRC1 off in full ASC during our first lock attempt, since it seemed to be wandering off. But, we lost lock in MOVE_SPOTS, probably because we weren't by-hand making the SRM follow along (since the beam diverters were closed so we didn't really have anything to track with). Second lock I left SRC1 on in full ASC, and things went fine and we got all the way to NLN.

The squeezer guardian is stuck in LOCK_OPO. I tried once setting the SQZ_MANAGER to DOWN and again to FREQ_DEP_SQZ, but it's still not happy. Since this is not what we were trying to test today (we were just seeing if the Yend DAC swaps worked), I'm just leaving the SQZ_MANAGER in DOWN.

We did, at Jeff's suggestion, have the VIOLIN_DAMPING guardian paused, since we didn't want to do bad things to violin modes if there was a big phase change with the new DAC. However Daniel estimates that we should see about a 10 degree phase shift at 1kHz, and a much smaller shift at 500 Hz, so I've just unpaused that guardian and the modes seem to be damping fine.

I am leaving the IFO locked, but requested ISC_LOCK to DOWN, so that if it does lose lock, it won't try to re-lock. This, and the lack of squeezing, means that I am not setting the Observing bit.

H1 SUS - Maybe seeing fuzziness in ETMY oplevs

jenne.driggers@ligo.org — Mon, 01 Dec 2025 17:46:51 -0800

Author: jenne.driggers@ligo.org

Report ID: 88297

[Jenne, Oli]

I'm intermittently, while we're locking, seeing some fuzziness on the ETMY oplev (first 2 attachments, with 'fuzzy'). Oli did a brief check, and while they find a different behavior that is present 4 days ago and today (3rd and 4th attachments, with 'drop'), at least a quick glance isn't finding the fuzziness that I'm seeing. We haven't looked at enough past data to say whether this is new, but it doesn't seem to be hindering our ability to lock, so I think we're fine to go forward with ETMX tomorrow.

Images attached to this report

H1 ISC - Comment to Change of reflected power from OMC during DARM offset step

jennifer.wright@ligo.org — Mon, 01 Dec 2025 17:27:06 -0800

Author: jennifer.wright@ligo.org

Report ID: 88296

Correction to above calculation where I made a mistake in how to calculate P_00_arm:

The mode-matching, MM, of the OMC to the differential arm mode is defined as:

P_00_arm / ( P_HOM_arm + P_00_arm )

The power from higher order modes of the carrier from the differential arm motion can be calculated using:

P_HOM_arm = P_REFL - d - (R_cav*P_00_arm)

In order to calculate P_00_arm we need to use the measurement of contrast defect which can be obtained from our Sep 4th DARM offset measurements by running

python /ligo/gicommon/labutils/darm_offset_step/plot_darm_optical_gain_vs_dcpd_sum.py

on the offset step data we took on Sep 4th (see LHO alog #86744). This code plots the P_AS vs. P_DCPD graphs I mentioned in that alog, but also works our how the optical gain changes from the PCAL line height changes in DARM as the offset is changed. The plot of P_DCPD vs. optical gain has a minimum where the optical gain is zero and the power level here is considered the contrast defect (P_00_cd * T_cav) in our notation.

The contrast defect for the 255 Hz line is 1.202 mW for the partially thermalised interferometer and 1.268 mW for the fully thermalised interferometer.

Then we can obtain the power in the carrier from differential arm motion as:

P_00_arm = (P_DCPD - contrast defect)/T_cav

If we do this calculation for the half-way thermalised measurement we get

MM = 0.9978

For the fully thermalised case we get:

MM = 0.9981

The code to calculate this: Calculate_refl_power.py located at /ligo/home/jennifer.wright/git/2025/DARM_OFFSET/ has been updated.

Non-image files attached to this report

darm_optical_gain_vs_dcpd_power_gps_start_1441050554_Sep_4th__1_hr_25_mins_into_lock.pdf

darm_optical_gain_vs_dcpd_power_gps_start_1441056274_Sep_4th__2_hrs_59_mins_into_lock.pdf

X1 DTS - SPI Pathfinder, Phase noise measurements for Keysight 33600A waveform generator

joshua.freed@ligo.org — Mon, 01 Dec 2025 17:16:00 -0800

Author: joshua.freed@ligo.org

Report ID: 88293

J. Freed,

I took Phase noise measurements of the 2 channel Keysight 33600A waveform generator for its use in building SPI Pathfinder in the optics lab before install. Going only off of the phase noise graphs, it is sufficient as it shows comparable results to the SRS which had a phase noise considered to be good enough for SPI pathfinder.

Key.png Shows the phase noise results. C1, C2 are the phase noise results for Channel 1 and Channel 2 on the Keysight, respectively. (Set up shown below). Shown for comparison the SRS SG392, which was suggested as a possible frequency source for SPI. The last measurement shown is the direct measurement of phase noise between the 2 channels of the Keysight. This measurement reflects the intended use case of the Keysight for SPI. As we need 2 frequencies at slightly different frequencies locked to each other and SPI will be measuring the output phase difference. Note the 60Hz peak; most likely caused by unclean AC power. This is why we are not using an AC powered device in the final installation.

Screenshot2025-12-01at50150 PM.png Shows the setup for C1, and C2. measurements. The SRS value was found with the same set up, just replacing the Keysight 33600A with a SRS. The C1-C2 is a direct measurement by plugging both channels into the BluePhase 1000. There is no 10MHz Ext back attachment in this measurment in order to best represent Keysight's theoretical performance in the optics lab.

Images attached to this report

LHO General - Ops Day Shift Summary

ryan.short@ligo.org — Mon, 01 Dec 2025 17:08:24 -0800

Author: ryan.short@ligo.org

Report ID: 88294

TITLE: 12/02 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY: Busy day upgrading DAC cards at EY. After suspensions were recovered, we wanted to relock the IFO to ensure the new DACs haven't introduced a problem, so I started an initial alignment. Unsurprisingly, ETMY and TMSY needed quite a bit of adjustment, but otherwise alignment went smoothly. Locking the IFO presented a couple of issues; after DRMI locked, I needed to turn of the SRC1_P loop as it appeared to be pulling alignment away. I turned this off again during ENGAGE_ASC_FOR_FULL_IFO as it appeared to be misbehaving for the second time. Eventually H1 lost lock during MOVE_SPOTS, but we're unsure as of yet what the cause was. H1 is attempting to lock again under the supervision of a few folks still here in the control room.
LOG:

Start Time	System	Name	Location	Lazer_Haz	Task	Time End
15:46	FAC	Eric	FCES	N	Checking air handler	16:19
16:12	FAC	Nellie	MY	N	Technical cleaning	17:01
16:16	FAC	Kim	MX	N	Technical cleaning	16:56
16:27	CDS	Fil	EY	N	AI chassis modifications	20:50
16:46	FAC	Tyler, McD Miller	FCES	N	Air handler fix	19:19
17:01	FAC	Kim	H2	N	Technical cleaning	17:12
17:12	FAC	Nellie	Opt Lab	N	Technical cleaning	17:29
17:52	CDS	Daniel	CR	N	Beckhoff updates	19:19
17:52	SEI	Jim	Remote	N	Testing on HAM6 ISI	19:52
18:20	ISC	Kar Meng	Opt Lab	Local	OPO work	19:18
18:52	PEM	Rene, Alicia	CER	N	Moving magnetometer	19:02
20:21	CDS	Dave	EY	N	DAC card replacement susey	20:50
20:25	TCS	RyanC	MER	N	TCS chiller checks	20:32
20:36	AOS	Betsy	Opt Lab	N	Rearranging parts	21:28
20:44	JAC	Jennie	LVEA/Prep Lab	N	Grabbing parts then JAC table work	21:42
21:12	CAL	Tony	PCal Lab	N	Measurement setup	21:19
21:13	ISC	Kar Meng	Opt Lab	N	Looking for electronics	21:28
22:05	ISC	Jennie	LVEA/Prep Lab	N	JAC table work, maybe getting more parts	22:33
22:32	FAC	Tyler	Hi-bay	N	Loading scissor lift into hi-bay	23:30
00:47	PEM	Rene, Alicia	CER	N	Moving magnetometer	00:54

H1 CDS - Comment to h1susey upgrade to LIGO-DACs

jonathan.hanks@ligo.org — Mon, 01 Dec 2025 16:56:51 -0800

Author: jonathan.hanks@ligo.org

Report ID: 88295

With the daqd restarts we made a few changes.

This is the first restart with the daqd0 leg re-configured
- Updated the restart scripts for the 0 leg to restart fw0 first and then the rest (tw0, nds0, gds0)
- Updated the pause between starting fw0 and starting the other systems as the fw takes longer to start up.
Removed a old compatibility flag from the daqdrc on fw0 and fw1.
- Removed the "USE_BROKEN_CONFIGURATION_NUMBER_HASH" line. This is only needed for compatibility with older daqds and can be turned off if it is turned off on all daqd fw systems at the same time. This deals with how the configuration hash is created, this hash value represents the channel list. The hash is then sent to the run number server to get the configuration/run number to put in the frame.
Removed 8 channels from the GDS broadcaster list.
- H1:FEC-98_DAC_OVERFLOW_ACC_2_[0,1,2,3]
- H1:FEC-98_DAC_OVERFLOW_ACC_3_[1,2,3,4]

We did two restart passes as h1susetmypi needed an updated to deal with DAC changes.

H1 CDS - h1susey upgrade to LIGO-DACs

david.barker@ligo.org — Mon, 01 Dec 2025 16:46:57 -0800

Author: david.barker@ligo.org

Report ID: 88292

Richard, Jonathan, Fil, Marc, Daniel, EJ, Jeff, Oli, Ryan S, Dave:

h1susey was upgraded from Gen Std DACs (3x18bit, 2x20bit) to 2 LIGO-DACs.

Fil upgraded the three AI chassis to use the new SCSI interface board.

We removed the old Gen Std DACs and installed the two new LIGO-DACs.

The first LIGO-DAC drives the first standard AI, which in turn daisy-chain drives the second standard AI.

The second LIGO-DAC drives the special PI AI chassis.

After the hardware was changed the new h1iopsusey, h1susetmy, h1sustmsy and h1susetmypi models were rev-lock built and installed. A common model change for h1susetmy was accepted for its build.

EJ did a custom build for h1iopsusey due to rev-update issues found for watchdog source files. The user models were built with the production RCG-5.5.2

Following the model starts, the DAQ was restarted for new INI files due to removed DACs in h1iopsusey and h1susetmy.

H1 SUS - Comment to h1susey DAC Upgrade: Added ESDOUTF_LF and _RT filter banks susetmpi models' library part; h1susetmypi model now has it

oli.patane@ligo.org — Mon, 01 Dec 2025 16:42:14 -0800

Author: oli.patane@ligo.org

Report ID: 88291

Gain install alog: 88289

H1 SUS - Added/Updated DAC calibration filters in COILOUTF for TMSY and ETMY for new DACs

oli.patane@ligo.org — Mon, 01 Dec 2025 16:39:42 -0800

Author: oli.patane@ligo.org

Report ID: 88289

Jeff, Oli

Since the ETMY and TMSY electronics are now on 32CH, 28-bit DACs, we needed to add a calibration term that would account for the difference in bit count between the old and new DACs. The normal thing to do for these DAC upgrades is to add a gain in the COILOUTF filter banks that was gain(2^(NewBitCount-OGBitCount)). For example, during the conversion of ETMY L1/L2/L3 from their original 18-bit DACs to 20-bit DACs, the calibration was altered by the addition of a filter in their respective COILOUTF banks that was gain(4), since 2^(20-18) = 4.

This time, we needed the change in gain to be between the new bit count, 28, and the original bit count, 18, so gain(2^(28-18)) = gain(2^10)=gain(1024). These filters were added into the FM10 slot of ETMY_{M0,R0,L1,L2,L3}_COILOUTF and TMSY_M1_COILOUTF. In the case of ETMY L1/L2/L3, these gains overwrite the previous 20bitDAC filters since we don't need those anymore.

The other place where we needed to add these conversion filters was for ETMY PI, and even back in May 2025 Jeff had noticed that we had never added in any compensation for the 18-20-bit DAC upgrade (84522). To finally follow through on fixing that we added filter banks into the PI model (88285), which for ETMY PI are called H1:SUS-ETMY_PI_UPCONV_ESDOUTF_LF and H1:SUS-ETMY_PI_UPCONV_ESDOUTF_RT, and I added filters into FM10 for each that had that same gain(1024) in them. I also added these new filter banks to the PI medm screen (screenshot).

All these filters were loaded in, turned on, and accepted as on in safe sdf. We slowly turned everything back on, and it all looks to be working correctly.

CDS

Images attached to this report

LHO VE - Mon CP1 Fill

david.barker@ligo.org — Mon, 01 Dec 2025 16:14:38 -0800

Author: david.barker@ligo.org

Report ID: 88290

Mon Dec 01 10:08:07 2025 INFO: Fill completed in 8min 3secs

Images attached to this report

H1 SUS - h1susey DAC Upgrade: SUS Recovery Complete

jeffrey.kissel@ligo.org — Mon, 01 Dec 2025 16:04:18 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88288

J. Kissel, O. Patane ECRs: E2400409 and E2500296 IIET: 35739 and 35706, respectively WP: 12901 DWG: D1002741 After - Adding/updating DAC calibration compensation gains - Updating MEDM macros in order to confirm that DAC drive requests made it all the way out to the analog world on the right channels - Pausing guardians to make sure they didn't take control when we didn't want them to yet, - Making sure that all DAC requests were OFF - Untripping watchdogs and turning ON the MASTER SWITCH - Turning on small offsets to confirm those channel pathways were straight and linear, - Turning damping loops, one DOF at a time to confirm function and that they had roughly the right ~few second ring-down time - Turning on the alignment offsets to confirm that the whole suspensions move - Restoring all nominal ability for ISC output requests by resuming the guardian and running it from SAFE to ALIGNED a time or two, - Initiallizing new channels in SDF - Accepting differences in SDF (almost entirely the turning ON of calibration gains for the stages that were 18-bit DACs) We turned control over to the operations team with the words "all EY suspensions are confirmed functional and ready to use" at Dec 01 2025 ~15:45 PST (after having started at ~08:30 PST this morning; LHO:88274).

H1 SUS - PI guardian's gain reduced in guardian by 4x, to account for SUS work today

jenne.driggers@ligo.org — Mon, 01 Dec 2025 16:02:27 -0800

Author: jenne.driggers@ligo.org

Report ID: 88287

[JeffK, Jenne]

Jeff pointed out that the PI damping gain (if no changes were made to guardian) would now be 4x higher than they were throughout O4, due to the work done today. See alog 88285 for the actual work by Jeff and Oli. To account for this, the SUS_PI guardian now has a 1/4 in the gain setting line.

Details for remembering later:

In June 2020, we upgraded from 18-bit to 20-bit DACs, and as Jeff notes in alog 88285, we didn't have a place to nicely account for the effective gain change digitally in the PI damping path. Effectively, we should have put in a filter with gain of 4x to account for the number of bits changed. Since we didn't, we have been actuating PIs (assuming same digital gains) 4x less during O4 than we had been in O3. Not a huge deal, since we had PI dampers and PI damping settings that were effective.

With today's work, Jeff and Oli have put in a digital place to correctly account for the gain change with the new 28-bit DACs. To keep the 'accounting' neat and tidy, they've put in the whole correction gain from 18-bit to 28-bit (not just 20-bit to 28-bit). This means that they've put in the forgotten-during-O4 gain of 4x, so if things were left alone in the SUS_PI guardian, we'd be sending 4x actuation strength to the ETMs. In O4, the 4 PI modes we've been damping have only gone to the ETMs. Since we don't have automatic gain adjustment in the PI damping guardian, I've divided the gain setting line by 4 in SUS_PI, so that we'll end up with the same actuation strength now as we did have in O4.

ISC

H1 CDS - Comment to h1susey down for LIGO-DAC upgrade

jeffrey.kissel@ligo.org — Mon, 01 Dec 2025 15:52:09 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88286

"Yes, and..." to Fil's inventory and comments about what's changed within them -- AI Chassis D1000305 S1108084 (SUSEY-C1, slot U32) has now been transformed into a D2500353 AI chassis assembly AI Chassis D1000305 S1108070 (SUSEY-C1, slot U31) has now been transformed into a D2500353 AI chassis assembly AI Chassis D1500177 S1500300 (SUSEY-C1, slot U26) has now been transformed into a D2500400 AI chassis assembly

H1 SUS - h1susey DAC Upgrade: Added ESDOUTF_LF and _RT filter banks susetmpi models' library part; h1susetmypi model now has it

jeffrey.kissel@ligo.org — Mon, 01 Dec 2025 15:02:50 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88285

J. Kissel, O. Patane ECRs: E2400409 and E2500296 IIET: 35739 and 35706, respectively WP: 12901 DWG: D1002741 Oli was working their way through adjusting the SUS "OUTF" FM10 blocks that are traditionally used to adjust the calibration of the DACs being used, and we re-realized that we've never had a place in the PI model to adjust the DAC gain thru the upgrades from 18- to 20-, and now 28-bit DACs -- see the original discovery back in May 2025 (LHO:84522, which quotes that ETMY's PI DAC had been misalibrated by a factor of 4x since Jun 2020). In that May 2025 aLOG, I "mildly advocated" for an implementation of ESDOUTF banks like there is in every other SUS drive chain. Today, I implemented that change, since (a) the gain difference between a 18-bit and 28-bit DAC is now a factor of 2^10 = 1024x -- much more noticeable, and (b) it's a total no brainer change that's easy to do while we're already restarting this model for the DAC upgrade proper. The update to the library, /opt/rtcds/userapps/release/sus/common/models PI_MASTER_V2.mdl r26600 --> r34033 is within the ETM_UPCONV_V2 block, which I show in the attached BEFORE vs AFTER. We have compiled, installed, and restarted h1susetmypi front-end model so that it has this minor change. Oli will aLOG the installation of the gains.CDS, ISC, SUS

Images attached to this report

H1 CDS - Comment to h1susey down for LIGO-DAC upgrade

filiberto.clara@ligo.org — Mon, 01 Dec 2025 14:31:04 -0800

Author: filiberto.clara@ligo.org

Report ID: 88284

The following AI Chassis were updated:

AI Chassis D1000305 S1108084 (SUSEY-C1, slot U32)
AI Chassis D1000305 S1108070 (SUSEY-C1, slot U31)
AI Chassis D1500177 S1500300 (SUSEY-C1, slot U26)

The rear panel and DAC AI Interface Board D1000551 were removed. A new D2400308 LIGO DAC Anti Image Chassis Rear Panel and LIGO DAC AI Interface D2500097 were installed.

H1 SUS - SVN up'd ESD_LINEARIZATION_WITH_CHARGE Library Part; Inconsequential Change

jeffrey.kissel@ligo.org — Mon, 01 Dec 2025 14:22:22 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88283

J. Kissel, D. Barker As an inadvertent result of us using the new "rev lock" RCG feature during the build of front-end model h1susetmy, we discovered that there was a newer revision of the sub-sub library part used within the QUAD_MASTER library part -- /opt/rtcds/userapps/release/sus/common/models/ ESD_LINEARIZATION_WITH_CHARGE_MASTER.mdl : r16336 --> r30316 where the latter text shows the userapps svn repo version that the h1susetmy model was last compiled with, and what it will be compiled with if we use latest rev of the model (r34028, see LHO:88282). The ESD_LINEARIZATION_WITH_CHARGE_MASTER.mdl is *actually* a library, i.e. it contains a library of library parts that can be used for linearization. One is the ESD_LIN_CHARGE_MASTER, and the other is ESD_LINE_CHARGE_GENERIC_MASTER. We're 100.0% confident that the h1susetmy, which uses QUAD_MASTER, uses the ESD_LIN_CHARGE_MASTER block, that's poorly commissioned and has its settings configured to not use it. We're 98.5% that r16336 --> r30316 update to the library is the creation and commissioning of the other ESD_LINE_CHARGE_GENERIC_MASTER block, given Dec 2024 LLO aLOGs like LHO:74555 and 74771. The 1.5% lack of confidence is only that it's challenging to follow LLO's QUAD front-end model's references to libraries. Anyways -- this is just to say explicitly that we're going forward with using this r30316 version of the library, but it won't change any function or form of the h1susetmy model. CDS, ISC

Images attached to this report

H1 SUS - Comment to h1susey DAC Upgrade: SUS ETM / TMS Simulink Model Prep for 28-bit 32CH DACs

jeffrey.kissel@ligo.org — Mon, 01 Dec 2025 14:12:18 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88282

Here's the svn rev numbers for the versions I screenshot above /opt/rtcds/userapps/release/sus/h1/models/ h1susetmy.mdl r34028 h1susetmypi.mdl r34029 h1sustmsy.mdl r34030

H1 SUS - h1susey DAC Upgrade: SUS ETM / TMS Simulink Model Prep for 28-bit 32CH DACs

jeffrey.kissel@ligo.org — Mon, 01 Dec 2025 13:55:13 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88280

D. Barker, J. Kissel, O. Patane ECRs: E2400409 and E2500296 IIET: 35739 and 35706, respectively WP: 12901 DWG: D1002741 Following the solidifying of the wiring plan / IO chassis layout (see LHO:88276), Dave did the lion's share of updating the front-end USER models in prep to the 28-bit 32CH upgrade. I merely reviewed it to make sure we understood all the moving pieces and that the connections to the analog world made sense, and am documenting it here. Recall -- although the wiring diagram -v11 had shown all 20-bit DACs, in order to best reflect the 2022 ideal as of - TST stage :: ECR E1800306 / IIET: 11689, - PUM stage :: ECR E1900216 / IIET: 13232 - Everything else :: ECR E2100485 / IIET:20828, but H1 had not yet achieved that ideal, as we instead put our money toward developing and waiting for the 28-bit 32CH DACs. As such, in the "BEFORE" shots, you'll see the reality of the mix of 18-bit and 20-bit DACs. In short, the QUAD TOP (M0 and R0) and TMTS TOP (M1) had not yet been upgrade to 20-bit DACs. So those stages now "skip a version" and go straight to 28-bit 32CH DACs (D2200368). Attached are screen-shots of the DAC section of the user models BEFORE vs. AFTER: - h1susetmy BEFORE vs. AFTER - h1sustmsy BEFORE vs. AFTER - h1susetmypi BEFORE vs. AFTER I also include a view of the 28-bit 32CH DAC card usage from each model that uses it; a view which better shows the consumption of channels by function across USER models. - DAC0 AFTER - DAC1 AFTER This view helps identify some index / naming convention issues with DAC1 (see DAC1 usage screenshot). This DAC controls *only* the TST stage ESD, but spans the h1susetmy and h1susetmypi USER models. In both the susetmy and susetmypi models, the card_num parameter is set to 1 (one). HOWEVER, because the h1susetmy model uses both of the new two DACs (card_num=0 and card_num=1), the card_num=1's block name is DAC_1. In h1susetmypi which only uses the second card (card_num=1 ), it's block name is DAC_0. It's confusing when you look at it like this, and the RCG (current) forces it to be this way because of IO chassis which have mixed DAC card types (unlike ADCs, which the RCG will happily accept cherry pick ). The solution will be as it has been -- update the MEDM macro files that support the user interface, such that we get the UI showing the signal flow through the USER model output and IOP model output without folks having to think about it. CDS, ISC, SUS

Images attached to this report

H1 OpsInfo - Moved pump cart and bench near HAM 6

jennifer.wright@ligo.org — Mon, 01 Dec 2025 13:54:27 -0800

Author: jennifer.wright@ligo.org

Report ID: 88281

I need access to the two ISC/SQZ cheats of drawers that sit past HAM6 to get spare optomechanics to populate the in-air optics table for JAC.

There is a lot of stuff against this wall so I had to move a pump cart and table to get access to them. Checked with operator + Travis before doing this.

Let me know if I need to shuffle anything around.

Images attached to this report

H1 TCS - TCS Chiller Water Level Top-Off - Biweekly

ryan.crouch@ligo.org — Mon, 01 Dec 2025 12:35:35 -0800

Author: ryan.crouch@ligo.org

Report ID: 88279

Closes FAMIS27829, last checked in alog88104.

For TCSX I added 100mL to bring it from 30.3 to 30.4.

For TCSY I added 80mL to bring it from 10.3 to 10.4.

The dixie cup was empty.

H1 PEM - DustMon Monthly Trends

ryan.crouch@ligo.org — Mon, 01 Dec 2025 12:20:31 -0800

Author: ryan.crouch@ligo.org

Report ID: 88278

Closes FAMIS37258, last checked in alog86733

Everything's looking as expected, no followup investigations needed.

Images attached to this report

H1 SUS - h1susey DAC Upgrade: SUS ETM / TMS Wiring Diagram Updates -- D1002741

jeffrey.kissel@ligo.org — Mon, 01 Dec 2025 12:10:23 -0800

Author: jeffrey.kissel@ligo.org

Report ID: 88276

D. Sigg, D. Barker, F. Clara, O. Patane, J. Kissel ECRs: E2400409 and E2500296 IIET: 35739 and 35706, respectively WP: 12901 DWG: D1002741 Primary Change: Change the 18- or 20-bit 8CH DAC signal chains to 28-bit 32CH LIGO DAC chains - Consolidate all SUS signals driven by 5x 18- or 20-bit 8CH DACs (GS20AO8) onto 2x 28-bit 32CH DACs (D2200368) - Replace 18-/20- 8CH AI chassis assemblies (D1000305 and D1500177) with WD relays to 28-bit 32CH AI chassis assemblies (D2500353 and D2500400), which use the AI chassis back plane interfaces without the relays D2500097 - Upgrade representation of DACs on the signal connection page to show both DAC cards (D2200368) and DAC adapter cards (D2400014) - Update the graphical representation on the rack drawings page to show the new CARD arrangement in the SUS-C2 U25 IO chassis I've crafted a quick drawing of these primary changes, which are attached here, and Oli will post the official Altium version to -v12 D1002741 shortly. Clean-as-you-go changes: - Upgrade representation of ADCs on the signal connection page to show both ADC cards (GS16AO16) and Adapter adapter cards (D0902496) - Updated the connections and labeling for AA chassis for ADC1 to better convey the connections as a pick-off and "parallel" relay of the Transmon QPD A signals (using ISC End Station Wiring Diagram D1100670 and pictures of SUS-C2 ETMX (S1301904) and SUS-C2 ETMY (S1301919). - Some name / connection clean-up on the graphical representation of the rack drawings - TMS TOP drivers were Triple Top, now they're correctly Transmon top.ISC

Images attached to this report

H1 PSL - PSL 10-Day Trends

ryan.short@ligo.org — Mon, 01 Dec 2025 12:06:41 -0800

Author: ryan.short@ligo.org

Report ID: 88277

FAMIS 31114

RefCav transmission and ISS diffracted power have been dropping a bit while PMC reflected power has been increasing, but otherwise no major events over the past week while the IFO has mostly been down.

Images attached to this report

LHO General - Comment to Ops Day Shift Start

ryan.crouch@ligo.org — Mon, 01 Dec 2025 10:50:54 -0800

Author: ryan.crouch@ligo.org

Report ID: 88275

I think Jenne meant to write Tuesday January 28th instead of the 25th which is a Saturday.

H1 CDS - h1susey down for LIGO-DAC upgrade

david.barker@ligo.org — Mon, 01 Dec 2025 08:52:30 -0800

Author: david.barker@ligo.org

Report ID: 88274

WP12901 LIGO-DAC upgrade

Daniel, Fil, Marc, Jonathan, Richard, EJ, Ryan S, TJ, Jeff, Oli, Dave:

h1susey was fenced and power down at 08:25 in preparation for its upgrade to LIGO-DACs. SWWD was bypassed on

Fil is at EY upgrading the AI chassis to accept the new SCSI links from the DACs.

H1 CDS - Matlab license file update pushed out to CDS

jonathan.hanks@ligo.org — Mon, 01 Dec 2025 08:47:31 -0800

Author: jonathan.hanks@ligo.org

Report ID: 88273

The matlab license file needed to be updated. I have updated the license files for the network installed copies.

We also copy a version of matlab onto the workstations to get a better startup time. I am pushing the update out to the workstations and laptops via puppet. This will have the updates out within the hour, however laptops will not get the update until they are up and puppet has run.

LHO General - Ops Day Shift Start

ryan.short@ligo.org — Mon, 01 Dec 2025 07:42:54 -0800

Author: ryan.short@ligo.org

Report ID: 88272

TITLE: 12/01 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
OUTGOING OPERATOR: None
CURRENT ENVIRONMENT:
SEI_ENV state: CALM
Wind: 2mph Gusts, 0mph 3min avg
Primary useism: 0.03 μm/s
Secondary useism: 0.23 μm/s
QUICK SUMMARY: Outdoor temps below freezing and foggy on-site. H1 has been down over the weekend and upgrades begin today with CDS work.

H1 CDS - Comment to FCES VEA temperature drop overnight

gerardo.moreno@ligo.org — Mon, 01 Dec 2025 01:39:40 -0800

Author: gerardo.moreno@ligo.org

Report ID: 88271

On a positive note the drop on temperature aides the internal pressure of all vacuum envelopes, internal to HAM8 and HAM8 annulus. See attached plot for internal pressure of HAM8 for a change of about 2.0x10^-08 Torr.

Images attached to this report