The "final answer" measurements are
2022-02-15_OMCDCPDTIA_MeasSetup_mag.TXT
2022-02-15_OMCDCPDTIA_MeasSetup_pha.TXT

2022-02-15_OMCDCPDTIA_OMCA_DCPDA_mag.TXT
2022-02-15_OMCDCPDTIA_OMCA_DCPDA_pha.TXT

2022-02-15_OMCDCPDTIA_OMCA_DCPDB_mag.TXT
2022-02-15_OMCDCPDTIA_OMCA_DCPDB_pha.TXT

There were several mistakes and misunderstands as we ramped up our understanding of this circuit, so you'll see files in the directory marked BADBAD. I keep them for future demonstrative purposed and/or to explore whether the data is "good enough" in the future fullness of time, in the limit of infinite person power.

Here're their explanations of what happened:
- When we first took the data, we forgot to turn the auto-offset off, and so at around ~1 Hz, there's a few frequency points where there's a drop in magnitude. Could confuse the fitter.
2022-02-14_OMCDCPDTIA_OMCA_DCPDA_AutoOffsetMidMeasBADBAD_mag.TXT
2022-02-14_OMCDCPDTIA_OMCA_DCPDA_AutoOffsetMidMeasBADBAD_pha.TXT

- When we resumed and re-installed the test setup the next day, the DB9 breakout board was not completely engaged, but we only discovered it when we saw the OMCA DCPDB transfer function show up with a factor of 2 less *AC* (~flat region between 10-1000 Hz) gain. Maybe this data set was OK, but the B data set was bad so we engaged the DB9 and retook the three sets.
2022-02-15_OMCDCPDTIA_OMCA_DCPDA_DB9BreakLooseBADBAD_mag.TXT
2022-02-15_OMCDCPDTIA_OMCA_DCPDA_DB9BreakLooseBADBAD_pha.TXT

- After taking the final MeasSetup results, we realized that the D2100630
	<https://dcc.ligo.org/LIGO-D2100630>
PCB drawing was *actually correct* and the test input actually *is* incorrectly pinned.
2022-02-15_OMCDCPDTIA_OMCA_DCPDA_DB9TestInputPosNegFlippedBADBAD_mag.TXT
2022-02-15_OMCDCPDTIA_OMCA_DCPDA_DB9TestInputPosNegFlippedBADBAD_pha.TXT
2022-02-15_OMCDCPDTIA_OMCA_DCPDB_DB9TestInputPosNegFlippedBADBAD_mag.TXT
2022-02-15_OMCDCPDTIA_OMCA_DCPDB_DB9TestInputPosNegFlippedBADBAD_pha.TXT
2022-02-15_OMCDCPDTIA_MeasSetup_DB9TestInputPosNegFlippedBADBAD_mag.TXT
2022-02-15_OMCDCPDTIA_MeasSetup_DB9TestInputPosNegFlippedBADBAD_pha.TXT

- So then, we flipped the clip leads to the correct pins, and retook all the data. That's the "final answer" data listed above.

SR785 Settings for the "final answer data"

	Display Options
	Live
	Dual
	X-axis logarithmic
	RPM Frequency OFF
	Grid ON
	Grid Div 10
	Nyquist grid (irrelevant)
	Phase suppress 0.000
	d/dx window 0.5% (irrelevant)


	Display Setup
	Measurement group - swept sine
	Measurement - freq. resp
	Upper Display
	View - Lin mag
	Units - dB off
		peak - off
		phase - 
		dBm ref. imp.- 50
	Lower Display
 	View - Phase
 	Unit s- deg

	Source
	Auto level Ref - off
	Amp - 4V_pk
	Source ramp - on
	Ramp rate - 5 V/s
	Offset - 0

	Freq
	Start - 100 mHz
	Stop - 102.4 kHz
	Repeat - single shot
	Type - log
	AR - off
	Number of points - 200

	Input (Almost entirely the same
	      for both Ch 1 and Ch 2)

	Source - analog
	Channel - 1&2
		Input mode - A-B
		Ch1 coupling - DC
		Input range - 14 dbV Ch 1; 16 dbV Ch 2
		AA filter - On
		Whitening- Off
		Autorange - Up only
	AUTO OFFSET: OFF.

Averages
	Settle time - 11.719 ms << this was just what was there, 7.8125 ms is also fine, but maybe we also consider making it longer to decrease the frequency where "settling" switches from Settle Cycles to Settle Time, since 1/11.719 ms =  85 Hz, and 1/7.8125 ms =  128 Hz. No idea why these times are specified to the [usec] level.
	Settle cycles - 5 << this was too many made the measurement 1.5x longer than it needed to be! Can reduce to 2.
	Integration time - 152.34 ms
	Integration cycles - 5