%%% OLD OLD OLD %%% filter switching set to Input "Zero History" and Output "Immediately" SimAcqOFF # DESIGN ETMY_L2_COILOUTF_UL 0 zpk([11.8700], [119.6200], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 0 zpk([11.8100], [120.0700], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 0 zpk([11.8400], [119.6800], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 0 zpk([12.7500], [118.3800], 1, "n") SimAcqON # DESIGN ETMY_L2_COILOUTF_UL 1 zpk([1.3100], [106.1200], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 1 zpk([1.3000], [106.4200], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 1 zpk([1.3000], [105.4300], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 1 zpk([1.4500], [106.2100], 1, "n") SimLP # DESIGN ETMY_L2_COILOUTF_UL 2 zpk([5.6200; 21.4100], [0.5000; 240.8600], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 2 zpk([5.7000; 21.6600], [0.5000; 242.8200], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 2 zpk([5.7400; 21.3800], [0.5000; 241.1500], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 2 zpk([5.7800; 21.0900], [0.5000; 239.5100], 1, "n") AntiAcqOFF # DESIGN ETMY_L2_COILOUTF_UL 5 zpk([119.6200], [11.8700], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 5 zpk([120.0700], [11.8100], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 5 zpk([119.6800], [11.8400], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 5 zpk([118.3800], [12.7500], 1, "n") AntiAcqON # DESIGN ETMY_L2_COILOUTF_UL 6 zpk([106.1200], [1.3100], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 6 zpk([106.4200], [1.3000], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 6 zpk([105.4300], [1.3000], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 6 zpk([106.2100], [1.4500], 1, "n") AntiLP # DESIGN ETMY_L2_COILOUTF_UL 7 zpk([0.5000; 240.8600], [5.6200; 21.4100], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 7 zpk([0.5000; 242.8200], [5.7000; 21.6600], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 7 zpk([0.5000; 241.1500], [5.7400; 21.3800], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 7 zpk([0.5000; 239.5100], [5.7800; 21.0900], 1, "n") %%% NEW NEW NEW %%% filter switching set to Input "Always ON" and Output "Zero Crossing" SimAcqOFF # DESIGN ETMY_L2_COILOUTF_UL 0 zpk([12.1803],[113.6837], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 0 zpk([12.3093],[114.7967], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 0 zpk([12.3441],[115.0118], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 0 zpk([12.0803],[112.4055], 1, "n") SimAcqON # DESIGN ETMY_L2_COILOUTF_UL 1 zpk([1.3617;3.5809;144.8768],[3.576;76.4377;166.1999], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 1 zpk([1.3749;77.0526;145.2179],[76.9103+i*0.0061;76.9103-i*0.0061;166.635], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 1 zpk([1.3616;2.4500;146.0432],[2.4426;76.4422;166.7998], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 1 zpk([1.3603;1.8388;143.3509],[1.8202;76.1815;165.2128], 1, "n") SimLP # DESIGN ETMY_L2_COILOUTF_UL 2 zpk([3.3488;27.2313;108.1098],[2.4192;3.3597;1207.2547], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 2 zpk([2.2592;27.5952;109.4840],[2.2436;2.4807;1220.5785], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 2 zpk([3.4359;27.6321;108.3918],[2.4543;3.4491;1209.9594], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 2 zpk([3.0491;27.9953;107.5277],[2.4829;3.0633;1201.2130], 1, "n") AntiAcqOFF # DESIGN ETMY_L2_COILOUTF_UL 5 zpk([113.6837],[12.1803], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 5 zpk([114.7967],[12.3093], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 5 zpk([115.0118],[12.3441], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 5 zpk([112.4055],[12.0803], 1, "n") AntiAcqON # DESIGN ETMY_L2_COILOUTF_UL 6 zpk([3.576;76.4377;166.1999],[1.3617;3.5809;144.8768], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 6 zpk([76.9103+i*0.0061;76.9103-i*0.0061;166.635],[1.3749;77.0526;145.2179], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 6 zpk([2.4426;76.4422;166.7998], [1.3616;2.4500;146.0432],1, "n") # DESIGN ETMY_L2_COILOUTF_LR 6 zpk([1.8202;76.1815;165.2128],[1.3603;1.8388;143.3509], 1, "n") AntiLP # DESIGN ETMY_L2_COILOUTF_UL 7 zpk([2.4192;3.3597;1207.2547],[3.3488;27.2313;108.1098], 1, "n") # DESIGN ETMY_L2_COILOUTF_LL 7 zpk([2.2436;2.4807;1220.5785],[2.2592;27.5952;109.4840], 1, "n") # DESIGN ETMY_L2_COILOUTF_UR 7 zpk([2.4543;3.4491;1209.9594],[3.4359;27.6321;108.3918], 1, "n") # DESIGN ETMY_L2_COILOUTF_LR 7 zpk([2.4829;3.0633;1201.2130],[3.0491;27.9953;107.5277], 1, "n") AntiAOSEM # DESIGN ETMX_L2_COILOUTF_UL 8 zpk([131.0161;1175.8141],[125.6849;834.3799;1751.1282],1,"n") # DESIGN ETMX_L2_COILOUTF_LL 8 zpk([121.2433;869.6445;2361.2862],[116.6856;723.2315;1341.4576;2736.4936],1,"n") # DESIGN ETMX_L2_COILOUTF_UR 8 zpk([129.1906;1192.9006],[123.9290;834.9612;1825.0572],1,"n") # DESIGN ETMX_L2_COILOUTF_LR 8 zpk([127.5633;1198.3934],[122.4376;837.1883;1845.9303],1,"n")