Displaying report 1-1 of 1.
Reports until 19:46, Tuesday 04 March 2014
H1 ISC (ISC)
evan.hall@LIGO.ORG - posted 19:46, Tuesday 04 March 2014 - last comment - 09:15, Wednesday 05 March 2014(10509)
PRCL measurement: no success yet

[Ed, Yuta, Stefan, Arnaud, Sebastien, Jeff, Evan]

Temperature loop

On Sunday, Stefan helped me get a stable temperature loop going for the auxiliary laser PLL. The lasers now stay frequency-locked for about 5 minutes. We take the fast control signal, feed it into an SR560 for gain/rolloff control, then attenuate a bunch, and feed it into another SR560 which sums this signal with a trimpot-controlled DC offset signal. This signal then goes into the slow control of the laser. I suspect the short lock time is due to the fact that the SR560 has no integrating feature; right now I've just set it to have a DC gain; the pole of the temperature loop is set by the thermal pole of the laser. A diagram of the loop topology will be uploaded soon.

PRMI FSR sensing: no success

On Monday, the EE shop made me a 60-ft BNC cable with LMR-195. I used this to take the raw RF signal from REFLAIR_B and bring it over to the IOT2R setup. This signal is demodulated using the PLL offset frequency as the LO, and the resulting DC trace is monitored on a scope.

This afternoon, Yuta and I stole time from the green team in order to lock PRMI and try to see if the demodulated REFLAIR_B signal would show any kind of error signal in response sto the PLL offset being swept across an FSR of the PRC. We swept from 58 MHz to 62 MHz, but did not see a clear DC response from this error signal; the DC was between -1 mV and 0 mV, with an rms noise of a few hundred millivolts. If the offset frequency was set to be near a harmonic of 9.1 MHz, the error signal would become dominated by the beat of the harmonic against the offset frequency (as one would expect).

Next, we tried looking at POPAIR_B_LF to see if we could see a DC power buildup as a function of PLL offset. We didn't see anything; the DC power fluctuated between 70 and 90 counts at all times, and showed no change in response to the PLL offset.

Addendum on PRMI Iocking

Yuta tried for some time this afternoon to get PRMI locked. The biggest stumbling block was that PRY showed no fringes. Eventually, with the help of Arnaud, Sebastien, and Jeff, it was realized that

  1. ISI target values (e.g. H1:ISI-BS_ST1_CPS_RZ_TARGET) change after each CDS reboot; they must be corrected by hand. BS ISI stage 2 Rz was particularly bad.
  2. Changing the signal blending from 'Start' to 'TCrappy' for BS ISI stage 1 and turning stage 2 off helps locking PRMI. When ISI settings were wrong, power recycling gain showed large fluctuations at ~0.5 Hz (presumably from the microseism), with a modulation depth of about 50%.
Comments related to this report
evan.hall@LIGO.ORG - 09:15, Wednesday 05 March 2014 (10523)

A schematic of the PLL loop and a diagram of the table are attached.

Images attached to this comment
Non-image files attached to this comment
Displaying report 1-1 of 1.