J. Kissel, C. Cahillane, J. Driggers

Today we explored some of the potential systematics in using the ALS DIFF VCO to calibrate the DARM ETM actuation scale factor, as has been done prior to ER7 (see LHO aLOG 18711). Specifically, we've tried to precisely measure the frequency dependence of the the famous z:p = (40:1.6) [Hz] filter just before the low-noise VCO (see LowNoiseVco, and D0900609). However, because the VCO (an MFC9119-10) is a non-linear actuator, it must be locked to a carrier frequency. We want the carrier to be what is nominally used to control the arms during ALS DIFF using the same Phase-Locking Loop (D1300812) and Frequency Difference Divider (see T1400317) to remain in the regime where we get the same amount of [Hz/ct] out of the PLL's control signal.

I attach a PDF of the entire system which is a copy of what was discussed in T1500383. Also attached are plots of the measurement.

The idea: 
- Lock the PLL to an independent frequency reference (a marconi in the CER) in place of the DIFF RFPD input to the Phase-Frequency discriminator. The IFR carrier is tuned to be of frequency roughly the nominal ALS DIFF frequency 157.84 [MHz], but refined further to make the H1:ALS-C_DIFF_PLL_CTRL_INMON as close to zero as possible. It's that PLL_CTRL signal that's used as an error signal for the ALS DIFF arm feedback when ALS DIFF is locked. Today, the carrier was tuned to 157.783 [MHz] to minimize PLL_CTRL. Again, this ensures that the [Hz/ct] of the DIFF_CTRL_INMON signal (or more precisely the VCO itself) remains in the linear regime exactly surrounding the carrier frequency we use for during a nominal ALS DIFF lock.
- Measure the PLL Open Loop Gain TF, using an SR785 connected to the PLL (whose inputs are in the back of the rack); Source -> EXC, Test2 -> Ch1A (Ch1B 50 [Ohm] terminated), Test1 -> Ch2A (Ch2B 50 [Ohm] terminated). Once we have the Open Loop Gain transfer function -- down to the very *very* low frequency of ~1 [Hz], then we can model the entire loop, extracting out all of the frequency dependence -- namely, the 40:1.6 Hz filter.

It turns out, measuring this OLGTF is hard and time consuming, given the extreme amount of gain the loop has at low frequency. In other words, in the nominal configuration, with a 55 [kHz] UGF loop and boosts, the PLL is *very* good at suppressing your 10 [Vpp], ~1-100 [Hz] excitation, so you have to drive at the limit of your analog driver, and integrate for a very long time. Indeed, the only way to get *any* coherence below ~1 [kHz] is to turn the boosts OFF.

As such, we took a ~2 [hr] long TF of the loop with boosts OFF, and then characterized the boosts independently.

Craig and I continue to model the results, but the GPIB templates for the measurements, the measurements themselves, and notes on the measurements live here:
/ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/PreER8/H1/Measurements/ALSDIFF/2015-08-09/
# notes
Notes_ALSdiffPLL_9Aug2015.txt

# templates
TFSR785_DiffBoostsOLGTF_10_100k_09Aug2015.yml
TFSR785_DiffPLLOLGTF_0p5_200_09Aug2015.yml
TFSR785_DiffPLLOLGTF_100_100k_09Aug2015.yml

# olgtfs
PLLOLGTF/TFSR785_09-08-2015_144001.txt   << High Freq, Boosted
PLLOLGTF/TFSR785_09-08-2015_144447.txt   << High Freq, No Boosts
PLLOLGTF/TFSR785_09-08-2015_155915.txt   << Low Freq, No Boosts

# boost TFs
PLLBoostTF/TFSR785_09-08-2015_190215.txt   << Boost 1, z:p = (2k:40) [Hz]
PLLBoostTF/TFSR785_09-08-2015_185858.txt   << Boost 2, z:p = (17k:2k) [Hz] 

As it stands, the UGF of the ALS DIFF PLL (in the nominal, boosted configuration) is 54.8 [kHz], with a phase margin of 48 [deg].

Many thanks to Jenne for her help today!