J. Kissel, D. Tuyenbayv

After a quick look at the results from the UIM driver measurements taken for calibration purposes (see LHO aLOG 20846), and hearing similar whisperings of confusion from Darkhan in his detailed fitting analysis (progress continues, aLOG pending), I got the chance yesterday to quickly take a look myself to confirm my initial suspicions about the FAST I MON response to DAC drive measurements we took, and how they're "missing" the 85:300 zero:pole pair; see LHO aLOG 21127. I drove myself nuts for a half-a-day trying to reconcile the overall gain on the UL coil with what was expected to be sure *that* was right -- assuming it would provide clues if I couldn't reconcile it. I couldn't. 

I subsequently measured the respose of all UIM drivers of all QUADs and confirm that I was not insane. While the jury is still out on my sanity, at least I can confirm that
- The FAST I MON / TEST L EXC response for all four coils on all four of the Modified UIM Drivers are missing the expected 85:300 Hz zero:pole pair 
  EDIT: This is because the FAST I MONs are immune to this frequency response. See Below.
- This measurement techniue reports a factor ~2 less drive strength on the ETMY UL and LR channels, likely a busted monitor board.
- ITMY's UR and LR monitor board signals are total hosed.
I'll update the Integration Issue #9 with the later two bits of information.

EDIT: Why are the FAST I MONs Insensitive to the 85:300 [Hz] zero:pole pair? Turns out I just can't follow my own math. As it clearly states in My Notebook, you need to divide the current monitor by the output impedance -- i.e. whatever's in-between the voltage monitor pick-off and the coil current pick-off. Hence my equation I copied in LHO aLOG 21127,
                  R24_{MON}       1                   1     1       1      
DC calibration  = --------- x ---------- x G_{ADC} x --- x --- x ------- 
                  R25_{MON}   2 R5_{UIM}             E2O   CBG   G_{DAC} 
is wrong, and it should be
                  R24_{MON}       1                   1     1       1    
DC calibration  = --------- x ---------- x G_{ADC} x --- x --- x ------- 
                  R25_{MON}    2 Z_{OUT}             E2O   CBG   G_{DAC} 
where Z_{OUT} is formed by the whole R4, R5, and C12 ( = R27, R23, C26) network. This network is from where the 85:300 [Hz] zero:pole pair originates. Once I divided the transfer function with the right impedance -- voila! -- the 85:300 zero:pole pair appears.

The message again: The FAST I MONs are immune to the very frequency response we want to measure. So is every other monitor circuit, so we *have* to measure these drivers using analog electronics if we want to characterize this pole zero pair with any high precision than calculating what it should be from the component values. That being said, I don't think we'll time for this. In its stead, in case we don't find time, I checked the relevant resistor values inside spare modified UIM driver, and they we *at worst* 0.3% discrepant for all four channels on the spare. It's *very* regrettable that the monitor board appears to be giving discrepantly low DC transconductance, because that begets suspicion that the compenents are wrong, but I would be MUCH more inclined to blame the monitor board than the actual coil driver circuit given that the coil balancing gains are so similar, and using the stage hasn't brought up any issue.

Importance of this in the big picture: this re-opens the mystery of the frequency-dependent residual seen between naive model and measurment in the early results of the UIM actuation strength in LHO aLOGs 21015 and 21049. 

Stay tuned for Darkhan's results fitting the coil driver response poles and zeros that *are* there. After O1, we'll look into perfectly compensating all of these electronics, so we never have to think about this again.