Now that we've cleaned up all of our systematics from the DARM model and released the O1 version (see LHO aLOG 22056, I've updated the diagram that explains how the actuation path clock cycle delay is derived, and also shows that the current value of 7 [clock cycles] or 427.3 [us] that was recently installed at both sites (LHO aLOG 21788) still does a fine job at approximating the total delay between the inverse sensing and actuation chains.
A good diagram on the timing of a hardware injection through the DARM path: LLO aLOG 22361