WP12901 Daniel, Marc, Fil, Jonathan, Richard, Jeff, Oli, EJ, Dave:
Following from Monday's success in upgrading h1susey to the new LIGO-DACs on Tuesday 02dec2025 we upgraded h1susex to use LIGO-DACs.
This was a slightly different upgrade compared to h1susey because for the past 18 months h1susex ESDs have been driven using an early version of the LIGO-DAC. The h1susetmx model was using the GenStd 18/20-bit DACs for the upper stages and the LIGO-DAC for the L3 and ESD. The other models (h1sustmsx and h1susetmxpi) continued to use the Gen Std DACs.
The ESD and PI drives were being driven by a single 20bit-DAC using the special PI-AI chassis (first 6 chans through standard filters and output via DB15, last 2 chans through PI filters and output via DB9). When we upgraded the ESD drives to the LIGO-DAC we retained the original PI-AI chassis for these signals and temporarily installed the spare PI-AI chassis for h1susetmxpi 20bit-DAC's exclusive use.
The original LIGO-DAC used the 8-channel interface card. This card took the 32 channels from the LIGO-DAC and outputed the first 8 using its onboard DB25 connector. The remaining 24 channels were distributed using 3 Header Slot Plates (each with a DB25) ribbon cabled to the interface card. To fit these into the chassis, we displaced the two BIO cards to A4-3 and A4-4.
The IO Chassis changes were then:
Remove first-gen LIGO-DAC card, its 8chan interface card and the 3 header slot plates.
Remove the 3 18bit-DACs and their interface cards
Remove the 2 20-bit DACs and their interface cards
Install 2 LIGO-DACs in A1-4 and A2-2 with their new LIGO-DAC interface cards
Move the 2 BIO cards back to A4-1 and A4-2.
Fil upgraded all the AI chassis for LIGO-DAC SCSI Connection, duplicating what was done at EY. The second LIGO-DAC drives the PI-AI chassis, the first LIGO-DAC drives the 2 standard AI chassis, now daisy chained together.
Temporary cabling from the original LIGO-DAC chans 16-31 looped over to h1iscex were removed.
LIGO-DACs ADDED
| DAC0 S2500451 | Interface card SN007 |
| DAC1 S2500456 | Interface card SN005 |
Cards Removed
| First Gen LIGO-DAC | S2400042 |
| LIGO-DAC Interface Card | "2" in marker pen |
| 18bit-DAC | 110425-32 |
| 18bit-DAC | 110425-22 |
| 18bit-DAC | 101208-74 |
| 20bit-DAC | 190219-10* |
| 20bit-DAC | 150311-01 (S1700286) |
| 18/20-DAC Interface card | S1200225 |
| 18/20-DAC Interface card | S1104340 |
| 18/20-DAC Interface card | S1201759 |
| 18/20-DAC Interface card | S1102690 |
| 18/20-DAC Interface card | S1102687 |
* 20bit-DAC installed into h1iscex, now suspect.
WP12901. Daniel, Jeff, Oli, Fil, Marc, Jonathan, EJ, Tony, Dave:
Summary:
Yesterday I replaced h1iscex's 18bit-DAC with a 20bit-DAC as part of the project to eliminate all 18bit-DACs from production. There is currently no indication that the 20bit-DAC is driving the AI chassis with any voltage, investigation is ongoing.
Details:
The 18/20 bit DACs use the same interface card, so for the upgrade I was able to pull the IO Chassis out half way with cables still attached to access the PCIe bus. I removed the old 18bit-DAC and replaced it with on of the 20bit-DACs from h1susex upgrade
| old 18bit-DAC (removed) | 110425-03 |
| new 20bit-DAC (installed) | 190219-10 |
I do not know if the 20bit-DAC from h1susex was the one driving the PI or the one which had been idle since the LIGO-DAC went in mid 2024.
The original interface card and ribbon cable were reused. No field cabling was disconnected, no AI chassis were powered down.
Upgrade was done between 12:00 and 13:00 Tue 02dec2025.
Later that afternoon Tony found that the PCAL readbacks were not responsive. Tony and I went to EX around 17:00 to verify the 20bit-DAC was installed and connected correctly, it was.
This DAC has a special AI Chassis, D1101785 "aLIGO 18 Bit AI Chassis" which has handy BNC pickoffs for all 8 channels. We put a scope on the two channels being driven by h1calex (6,7) and could see no signal.
Also the last channel on the AI is loop-backed to the first ADC AA chassis with a DB9 cable, and the IOP is configured by SDF to drive the duotone from DAC0-chan7 back to ADC0-chan30. No signal is seen there either since the upgrade.
DCC docs for "18bit AI Chassis"
D1101785 [front section]
D1200316 [whole chassis]
The "AI WD" green LED on the rear panel is ON when the serial cable from the DAC Interface cable is connected and OFF when the cable is disconnected, suggesting the DAC is driving the WD line correctly at least.
Model changes:
h1iopiscex (Dave) updated to new DAC configuration
h1calex, h1pemex (Jeff, Oli) updated to new DAC configuration
All models on this front end, including h1iscex and h1alsex, were built and installed with RCG-5.5.2
Tagging CAL and PEM because this is "their" DAC.
We've done the typically thing with a DAC upgrade:
- the DC calibration of the DAC has changed from (roughly) 20 / 2^18 [Vpp_differential / ct] to (roughly) 20 / 2^20 [Vpp_differential / ct]
- Such that upstream control systems "don't have to be retuned" we apply a digital factor of (exactly) 4.0x to all output signals for each DAC channel
As such, for example, the calibration of the PCAL actuation / excitation chain is likely now slightly different, and should be remeasured.
Tue Dec 02 10:01:28 2025 INFO: Fill completed in 1min 27secs
Does not look like a good fill. Will try again tomorrow
TITLE: 12/03 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
OUTGOING OPERATOR: None
CURRENT ENVIRONMENT:
SEI_ENV state: CALM
Wind: 5mph Gusts, 3mph 3min avg
Primary useism: 0.02 μm/s
Secondary useism: 0.27 μm/s
QUICK SUMMARY:
H1 was IDLE overnight (had troubles getting through DRMI and a few steps beyond yesterday afternoon/eve---see Oli's log). In the middle of an Initial Alignment. Then we'll see about locking...
Day #2 of Crane Inspection work continues: This morning will be work for the South Bay crane, but will also need pendant work; this should go until about noon. (Then remaining cranes would be: Filter Cavity End Station, Staging Bldg, and some gantry cranes.) Yesterday, rest of LVEA cranes were inspected as well as End & Mid Stations.
(it's been almost 15min and Green Arms are almost aligned from Initial Alignment.)
Got word there are issues for PCal at EX (after investigations by Tony & Dave last night).
After the alignment is done, Dave is going to restart models on h1iscex & then after that they will possibly swap back in the 18-bit DAC (after the 20bit DAC was installed yesterday).
The IFO has been trying to relock for a bit now, but we were having multiple locklosses, from DHARD_WFSx3, BS_STAGE2, and CARM_OFFSET_REDUCTION. Most of the locklosses looked sudden (based on quick look at buildups ndscope), but the last attempt, we started getting SRM saturations and the PR gain was moving all over the place. I remembered that Jenne and RyanS had been saying that SRC1 wasn't being cooperative yesterday (88298), so I turned off the SRC1 and SRC2 loops and that stopped the oscillation. Unfortunately, we lost lock soon after in DHARD_WFS. I was (am) about to go home so I've put the detector in IDLE for the night.
h1pemex was upgraded from an 18-bit to a 20-bit DAC today, so we needed to make sure we had a calibration correction. The new filter banks that Jeff had put in (88321) for the calibration correction are called H1:PEMEX_EX_DACOUTF_1, H1:PEMEX_EX_DACOUTF_2, H1:PEMEX_EX_DACOUTF_3, and H1:PEMEX_EX_DACOUTF_4. I installed a filter called 20BitDAC that was a gain(4) in FM10 of each of these filter banks, loaded them in, and turned them on along with the input/output/gain of the filter banks. I've accepted these changes in sdf safe
Similar to what Ryan C did (88311), I've updated the saturation threshold values for ETMX M0/L1/L2/L3 and TMSX M1 stages to align with the new 28-bit DACs. Changes have been comitted to svn as r34061
I've installed a Welch WOB-L 2546B-01 at each end station to replace the Gast 523 pumps that we have been using. I've set the pressure to -19inHg and checked the flow at the dust monitor on the floor was 2.8L/min. The new pumps are much quieter, ~84dB vs ~67dB, but at a lower frequency. I'll post more photos of the setup and more details tomorrow after we see how they run over night.
Following the Beckhoff updates today (see alog88317), several settings needed to be restored in CS_ISC, EX_AUX, and EY_AUX after the initial SDF wrangling that was done after all the upgrades were finished.
As a reminder (for myself and others), when a Beckhoff computer is restarted, its settings are brought back up according to an internal settings file on that computer, NOT according to the safe.snap SDF table, unlike a traditional frontend model. This means the SDF tables for the restarted Beckhoff computers (basically anything with SYS in the name) will show several differences, that in most cases should be REVERTED. It's also useful to check the not monitored channels for differences, as we found a few of those today, although they were mostly just picomotor settings. See attached screenshots.
TITLE: 12/02 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY:
Main activity of the day was the the SUS DAC swap at EX (with the addition of more CDS work at both end stations as well).
In parallel, there was also crane inspection work which initiated gate valve closures due to loads needing to be craned over the beam tubes in the LVEA. Then in the afternoon, it was decided to open the gate valves for locking (so we could see how the End Stations looked after their big changes today).
[Through today's recovery to relocking, there were several items which needed to be done. Had much help from many who made recovery fairly easy **knock on wood**.]
Towards the end of the shift, able to see light flashing in the arms, and started an Initial Alignment (one gotcha was during Scan Alignment of Green Arm alignment which made the ALSx + y guardian nodes red---Ryan and Oli were on top of it and able to get alignment back. Other than that, alignment completed with no other issues. Moved on to locking and locked DRMI pretty fast on the first attempt....unfortunately there was a lockloss at DHARD_WFS.
NOTES:
LOG:
GV5 and GV7 were soft closed at ~8:30am local time today to facilitate equipment craning for crane inspections. We also closed FC-GV 3&5 to isolate the FCT. They were opened at ~3pm local time at the completion of the vertex crane inspection.
Closing WP 12908
J. Kissel, D. Sigg, D. Barker ECR E2100485 ECR E2200401 WP 12901 Continuing on the deprecation of 18-bit DAC path (ECR E2100485), we upgraded the h1iscex's DAC0 card today from an 18- to a 20-bit DAC. One of the front-end models that use that DAC is the h1pemex model. Here's the before vs. after for the models. While there, I found and left the new ADC card from ECR E2200401's PEM sensor array expansion. I'd thought it was installed solely for characterizing the 32CH LIGO DAC, but it had only been temporarily used for that. It should be there! And also, the electric field meter ADC should also remain there. If the PEM team wants to account for the factor of 4x gain change in the DAC calibration, I installed new DACOUTF filters upstream of the GDS filters that are used to drive the DACs. The model has been committed to /opt/rtcds/userapps/release/pem/h1/models/ h1pemex.mdl : r28026 --> r34059
Same as 88289, we updated the DACs for ETMX and TMSX, so we needed to update the calibration gain to account for the difference in bits. I added 28BitDAC calibration gains for ETMX M0/R0/L1/L2/L3 and TMSX M1 in COILOUTF FM10 and got rid of any lingering 20BitDAC filters. I did the same for ETMX PI. I loaded these filters in and turned them on, and accepted them as on in sdf safe
Tuesday Maintenance day impact notes.
Due to Beckhoff upgrades and restarts the PCAL lasers were shutoff.
When Beckhoff came back up the PCAL Lasers oddly didn't come back up this time.
The H1:CAL-PCALX_LASERPOWERCONTROL voltage was set to 0. I took that back to 5V for both arms.
Turned H1:CAL-PCALX_LASERENABLE back on.
H1:CAL-PCALX_SHUTTERPOWERENABLE back on.
Arm specific Settings :
PCALX:
H1:CAL-PCALX_OPTICALFOLLOWERSERVOOFFSET was set back to 3.65V.
H1:CAL-PCALX_OPTICALFOLLOWERSERVOGAIN : 39.60 dB
PCALY:
H1:CAL-PCALY_OPTICALFOLLOWERSERVOOFFSET : 3.80 V
H1:CAL-PCALY_OPTICALFOLLOWERSERVOGAIN : 38.56 V
Hey future Tony, Today is the day the X Arm 18bit DAC was changed out for a 20bit as well.
I was not able to get PCALX excitations in DARM. The new 20 bit H1IOPSCEX DAC is then plugged into an 18 bit AI chassis. Dave and I went out to the End station and put an Oscilloscope on it to try and see any sort of excitation coming out of the 18 Bit AI chassis. No dice.
We will need to do more troubleshooting tomorrow.
Relvent Alog: https://alog.ligo-wa.caltech.edu/aLOG/index.php?callRep=88333
Dave and I went back down to EX and Swapped out a DAC in H1ISCEX, and the Excitations and Duotone started to work again.
DAC card that was put in on Tuesday : SN 190219-10 <- bad DAC
DAC card that was swapped in today : SN150311-01 This is the working DAC.
I have since put back the OFSPD offset and Gain back to their nominal settings listed above.
We switched to the spare slow controls computer that is running Windows 10 IoT Enterprise LTSC, 21H2 (OS build 19044.4780), and the most recent TwinCAT 3.1 (4026.19.0). This TwinCAT version uses a packet manager and has changed the install directory to C:\Program Files (x86)\Beckhoff\TwinCAT. It supports Visual Studio 2022 and the new Altium workflow.
One new "feature" is that the PLC boot project needs to be activated in a separate step (previous versions would do this automatically after a build). We updated the install scripts to accommodate this.
We also tried a new TcIoc that was linked against EPICS 7, but it crashed during SDF restore repeatedly. We reverted back to the previous version linked against 3.15.9.
J. Freed,
I took Phase noise measurements of the 2 channel Keysight 33600A waveform generator for its use in building SPI Pathfinder in the optics lab before install. Going only off of the phase noise graphs, it is sufficient as it shows comparable results to the SRS which had a phase noise considered to be good enough for SPI pathfinder.
Key.png Shows the phase noise results. C1, C2 are the phase noise results for Channel 1 and Channel 2 on the Keysight, respectively. (Set up shown below). Shown for comparison the SRS SG392, which was suggested as a possible frequency source for SPI. The last measurement shown is the direct measurement of phase noise between the 2 channels of the Keysight. This measurement reflects the intended use case of the Keysight for SPI. As we need 2 frequencies at slightly different frequencies locked to each other and SPI will be measuring the output phase difference. Note the 60Hz peak; most likely caused by unclean AC power. This is why we are not using an AC powered device in the final installation.
Screenshot2025-12-01at50150 PM.png Shows the setup for C1, and C2. measurements. The SRS value was found with the same set up, just replacing the Keysight 33600A with a SRS. The C1-C2 is a direct measurement by plugging both channels into the BluePhase 1000. There is no 10MHz Ext back attachment in this measurment in order to best represent Keysight's theoretical performance in the optics lab.
Edits to previous post. Graph: X axis label should be 'Frequency offset from 80MHz (Hz)' and y-axis label should be 'dbc'
Keyradwref.png and Keyradworef.png are the requirements for the phase noise of our oscilator with SPI having and not having a reference interferometer respectivly. In the final SPI pathfinder install, we will have a reference interferometer giving us much less stringent requirements on our oscialtors phase noise. But during the build, it may be nessisary to run tests without a reference interferometer, I plotted the without reference interferometer if that situation ever does come up.
Model Changes:
h1iopsusex (Dave) modified to new DAC configuration. SWWD section updated to new DAC cards
h1susetmx, h1sustmsx, h1susetmxpi (Jeff, Oli) updated to new DAC configuraiton.
All models built and installed with RCG5.5.2
The following AI Chassis were modified for installation of the LIGO 32 CH DAC:
AI Chassis D1000305 S1104367 (SUSEY-C1, slot U32, new assembly drawing D2500353)
AI Chassis D1000305 S1001202 (SUSEY-C1, slot U31, new assembly drawing D2500353)
AI Chassis D1500177 S1500299 (SUSEY-C1, slot U26, new assembly drawing D2500400)
The rear panel and DAC AI Interface Board D1000551 were removed. A new D2400308 LIGO DAC Anti Image Chassis Rear Panel and LIGO DAC AI Interface D2500097 were installed.