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Reports until 11:48, Wednesday 11 September 2024
H1 TCS (DetChar)
camilla.compton@LIGO.ORG - posted 11:48, Wednesday 11 September 2024 (80043)
HWS Lasers turned on again, HWS plates need to be reinstalled.

TJ, Camilla.

We turned on the HWS lasers via medm and the LVEA chassis, they came back with the same powers we turned them off with (1.7mW for Y and 3.2mW for X). Since we realigned SR3 to the pre-April alignment yesterday 80028, both beams are on the CCD cameras, picture. The HWS plates are still removed from when we started alignment work in 78083. We will need to replace these before getting HWS signals, then restart HWS code.

CO2X chassis tripped off with the "RTD or IR alarm" error when I turned on the HWS SLED chassis (same rack). Turned back on with no issue (keyed off/on, gate button). We've seen similar behavior before. These CO2 chassis are planning an upgrade as per FRS6639.

I found the LVEA, clean receiving entrance and EE bay lights still on, turned them off but they would have been on during observing since yesterday, tagging Detchar.

Images attached to this report
H1 ISC (SEI)
jim.warner@LIGO.ORG - posted 11:17, Wednesday 11 September 2024 (80042)
Another attempt at redistributing IMC gains, changes to IMC_LOCK & ISC_LOCK

There was an earthquake rumbling through the site from Papua New Guinea during commissioning this morning, so Sheila suggested we could try the IMC gain redistribution again, as we got several notifications of IMC splitmon saturations. To do this, we commented out the IMC power adjust decorator in the IMC_LOCK guardian, unfortunately  in the wrong state, so we again got bit by IMC_LOCK readjusting IMC fast gain while we were trying to change IMC fast gain and IN1 and IN2 gains. After losing lock and catching the error, the decorator was commented out in the ISS_ON state for IMC_LOCK, and the gain redistribution was added to ISC_LOCK's LASER_NOISE_SUPPRESSION state. Still waiting for the ground to calm down enough for the arms to stay locked, but we will try locking with the gain redistribution in this time.

 

 

H1 ISC
sheila.dwyer@LIGO.ORG - posted 10:03, Wednesday 11 September 2024 (80039)
optical gain comparison after OFI repair

I realized that there isn't an explict alog about this because Paul was asking, so I'm adding this trend to show that after the OFI repair our optical gain is better by about 2.1%, implying that the optical losses are reduced by 4.3%.  While the OM2 heaters is now off and was on before the vent, that didn't have a large impact on optical gain last time that we changed it in late June. 

Images attached to this report
LHO VE
david.barker@LIGO.ORG - posted 09:32, Wednesday 11 September 2024 (80038)
Wed CP1 Fill

Wed Sep 11 08:12:51 2024 INFO: Fill completed in 12min 47secs

Images attached to this report
H1 CDS
david.barker@LIGO.ORG - posted 08:26, Wednesday 11 September 2024 - last comment - 09:23, Wednesday 11 September 2024(80035)
CDS Maintenance Summary: Tuesday 10th September 2024

WP12069 New CDS NAT router test

Jonathan:

The new CDS NAT router was tested successfully. It has been left in place as the production machine. Details in Jonathan's alog.

WP12067 Add PEM ADC to h1iscey

Fil, Erik, Dave:

The additional PEM ADC was added to h1iscey's IO Chassis. At the same time the failed A2 Adnaco backplane in the chassis was investigated.

After replacing backplanes and swapping fibers the problem was traced to the Adnaco adapter card in the front end computer, specifically the PCIe slot it was in (slot7, left-most as viewed from rear of computer).

h1iscey does not have any Contec binary IO cards, so it was possible to skip PCIe-slot7 and temporarily only use three Adnaco adapter cards.

h1iopiscey model was modified to add the new ADC. A DAQ restart was required

WP12076 Add VACSTAT EPICS channels to DAQ

Dave:

A new H1EPICS_VACSTAT.ini was added to the DAQ. EDC+DAQ restart required.

WP12075 Add RACCESS UID EPICS channels to DAQ

Dave:

H1EPICS_RACCESS.ini was expanded to add the UID channels. EDC+DAQ restart required.

WP12059 Add CDS HW Status EPICS channels to DAQ

Dave:

H1EPICS_CDSHWSTAT.ini was added to the DAQ. DAQ+EDC restart required.

DAQ Restart

Dave:

The DAQ was restarted 12:01 0-leg, 12:05 1-leg for the above changes. EDC was restarted at 12:02.

No problems with the restart, no second GDS restarts were required.

h1digivideo3 cameras briefly offline

Dave:

While tracing the digital video servers ethernet cabling I discovered the WorkStation-VLAN ethernet cable in eth0 of h1digivideo3 was not fully seated and its cameras went blue-screen.

After Erik alerted me to the issue, I pushed the ethernet cable and it reseated with a satisfying snap and the images started streaming again.

Comments related to this report
david.barker@LIGO.ORG - 09:21, Wednesday 11 September 2024 (80036)

h1iscey bad PCIe slot7 FRS32088

david.barker@LIGO.ORG - 09:23, Wednesday 11 September 2024 (80037)

Tue10Sep2024
LOC TIME HOSTNAME     MODEL/REBOOT
08:57:28 h1iscey      ***REBOOT*** <<< Add ADC and Debug A2 in IO Chassis
08:59:10 h1iscey      h1iopiscey  
10:01:35 h1iscey      ***REBOOT***
10:03:17 h1iscey      h1iopiscey  
10:07:24 h1iscey      ***REBOOT***
10:09:11 h1iscey      h1iopiscey  
10:09:24 h1iscey      h1pemey     
10:09:37 h1iscey      h1iscey     
10:29:13 h1iscey      ***REBOOT***
10:30:57 h1iscey      h1iopiscey  
10:31:10 h1iscey      h1pemey     
10:31:23 h1iscey      h1iscey     
10:31:36 h1iscey      h1caley     
10:31:49 h1iscey      h1alsey     


12:01:46 h1daqdc0     [DAQ] <<< 0-leg restart
12:01:58 h1daqfw0     [DAQ]
12:01:58 h1daqtw0     [DAQ]
12:01:59 h1daqnds0    [DAQ]
12:02:07 h1daqgds0    [DAQ]


12:02:58 h1susauxb123 h1edc[DAQ] <<< EDC restart


12:05:00 h1daqdc1     [DAQ] <<< 1-leg restart
12:05:12 h1daqfw1     [DAQ]
12:05:12 h1daqtw1     [DAQ]
12:05:13 h1daqnds1    [DAQ]
12:05:22 h1daqgds1    [DAQ]
 

LHO General
ibrahim.abouelfettouh@LIGO.ORG - posted 07:43, Wednesday 11 September 2024 (80033)
OPS Day Shift Start

TITLE: 09/11 Day Shift: 1430-2330 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Observing at 150Mpc
OUTGOING OPERATOR: TJ
CURRENT ENVIRONMENT:
    SEI_ENV state: CALM
    Wind: 6mph Gusts, 4mph 3min avg
    Primary useism: 0.01 μm/s
    Secondary useism: 0.14 μm/s
QUICK SUMMARY:

IFO is in NLN and OBSERVING as of 14:16 UTC.

SQZ is not perfectly optimized just looking at DARM.

Planning on going into planned calibration from 8AM PST to 10AM PST (15-17 UTC)

H1 General
thomas.shaffer@LIGO.ORG - posted 06:39, Wednesday 11 September 2024 (80032)
H1 Assistance this morning, ALS Y not locking

The IFO timed out during initial alignment because ALS Y would not lock. Flashes were at 0.8 but it wouldn't catch. I tried to manually move ETMY, TMSY, and eventually ITMY, but I couldn't increase the height of the flashes. After about 30 min of fussing with it, it caught and stayed locked. I have no idea what was different though. 

Initial alignment has just finished and main locking has commenced.

H1 General
ryan.crouch@LIGO.ORG - posted 22:00, Tuesday 10 September 2024 (80026)
OPS Tuesday EVE shift summary

TITLE: 09/11 Eve Shift: 2330-0500 UTC (1630-2200 PST), all times posted in UTC
STATE of H1: Observing at 151Mpc
INCOMING OPERATOR: TJ
SHIFT SUMMARY: Easy automated acquisitions but some short locks following the SR3 move, 22 and 14 minutes, the 3rd lock we were able to survive. The low range check yielded high PRCL, CHARD_Y, and a little DHARD_Y (mostly just at low frequency, <20Hz) coherence with cleaned DARM. We've been locked for almost 5 hours. LLO is currently down due to the incoming tropical storm/hurricane.

Images attached to this report
H1 SQZ
victoriaa.xu@LIGO.ORG - posted 18:16, Tuesday 10 September 2024 (80031)
Re-aligned SQZ after SR3 move

Naoki, Vicky

We are back to observing after the SR3 move. For SQZ, we had to move quite a lot to get the SQZ LO loop to lock (Naoki mostly moved ZM5 yaw sliders around +200 urad).

PSAMS SDFs attached to get back to our recent values (not the single-bounce values we found this morning in lho80010, but what we used yesterday / last couple weeks). So ZM 4,5 strains = +5.5V, -0.8V as they were yesterday.

We weren't able to try these new values properly in full lock because

1) OPO TEC temperature was off, Naoki had to move the OPO TEC setpoint from 31.474 --> 31.457 (ie, lowered it by 0.017 degC). Noticed this because anti-squeezing was like 2-3 dB too low.
2) SR3 move meant a big alignment shift for SQZ, regardless of PSAMS settings. The new SCAN_ALIGNMENT plots now also include OMC_RF3_Q so we can compare whether this is a usable signal for SQZ ASC.

So now we're basically back to where we were this morning, after the sr3 move. We can try the single-bounce psams settings from lho80010 in full lock another time.

Images attached to this report
LHO General
ibrahim.abouelfettouh@LIGO.ORG - posted 16:31, Tuesday 10 September 2024 (80028)
OPS Day Shift Summary

TITLE: 09/10 Day Shift: 1430-2330 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Preventive Maintenance
INCOMING OPERATOR: Ryan C
SHIFT SUMMARY:

IFO is in PREVENTATIVE_MAINTENANCE as of 23:06 UTC

Post-Tues Maintenance

We’re trying to get to observing but waiting on SQZ Team to finish alignment. We've reached NLN twice now.

Locking started at 19:58 UTC where after our SR3 move, we went into initial alignment in prep for full IFO locking. Initial alignment finished at 20:37 UTC. It took a while because we had to move SRM to alignment with the new SRM and SR2 positions.

We fully automatically got to NLN at 21:18 UTC but lost lock 22 minutes later (21:41 UTC) for unknown reasons. We didn’t get to observing due to SQZ commissioning work happening at that time.

Following the lockloss, we were not able to lock X-Arm ALS, losing lock twice unexpectedly, prompting yet another initial alignment. This initial alignment stalled at SRC align, which was unexpected considering we just moved SRM to proper alignment manually at this state. Ryan C paused the state and apparently that was all that was needed in order for initial alignment to re-catch, finishing the process. Onto real locking.

We lost lock unexpectedly at CHECK_IR but in relocking, were able to lock DRMI without going through PRMI or MICH. We then fully automatically got to NLN for a second time. SDF Diffs from first NLN acquisition attached.

UPDATE 16:21 UTC:

We lost lock again from NLN during SQZ alignment, convincing me that perhaps the previous LL was also SQZ related. 14 min lock. On the bright side, it seems we are reliably locking to NLN following the SR3 movement.

Other:

Planned + Completed Tuesday Maint Activities (All times UTC)

Other/Opportunistic (All times in UTC):

LOG:

Start Time System Name Location Lazer_Haz Task Time End
23:58 SAF H1 LHO YES LVEA is laser HAZARD 18:24
14:43 FAC Karen Optics, Vac Prep Labs N Technical Cleaning 15:20
15:19 FAC Karen EY N Technical Cleaning 16:37
15:20 FAC Kim EX N Technical Cleaning 16:37
15:21 IAS Jason LVEA YES Faro Movement 15:58
15:21 CDS Fil EY N PEM Chassis Change 17:42
15:32 FAC Christina Receiving/Hi-Bay N Forklift recycling 18:46
15:32 VAC Jordan, Erik LVEA YES HAM6 RGA 16:03
15:34 FAC Nellie FCES N Technical Cleaning 16:36
16:06 VAC Jordan, Erik LVEA YES HAM6 RGA: Part 2 16:25
16:21 OPS TJ LVEA YES TCS Line Inspection 16:49
16:22 CDS Marc EX N DAC Transition from read only to read&write 17:55
16:37 SUS Betsy, Travis LVEA YES LVEA Chamber Sweep 17:25
16:38 IAS Jason, Mitchell LVEA YES FARO Work 18:51
16:45 FAC Tyler LVEA, MX, MY YES, N, N Routine 3IFO Checks 18:11
17:01 FAC Karen, Kim LVEA YES Technical Cleaning 18:24
17:29 SEI Jim LVEA YES Checking HAM1/2 cleanroom 18:27
17:55 FAC Chris LVEA YES Battery Maintenace 18:16
18:01 VAC Janos, Gerardo LVEA YES Capturing Photos 18:20
18:01 CDS Marc EX N DAC Transition Ctd. 19:11
18:17 FAC Chris FCES N Snorkel-lift Battery Maintenance 20:16
22:20 FAC Chris Optics Lab N Battery Check 20:20
Images attached to this report
H1 DAQ
daniel.sigg@LIGO.ORG - posted 16:15, Tuesday 10 September 2024 - last comment - 15:53, Thursday 12 September 2024(80023)
New DAC gain and delay measurements

Marc Daniel

We measured the gain and phase difference between the new DAC and the existing 20-bit DAC in SUS ETMX. For this we injected 1kHz sine waves and measure gain and phase shifts between the two. We started with a digital gain value of 275.65 for the new DAC and adjusted it to 275.31 after the measurement to keep the gains identical. The new DAC implements a digital AI filter that has a gain of 1.00074 and a phase of -5.48° at 1kHz, which corresponds to a delay of 15.2µs.

This puts the relative gain (new/old) to 1.00074±0.00125 and the delay to 13.71±0.66µs. The variations can be due to the gain variations in the LIGO DAC, the 20-bit DAC, the ADC or the AA chassis.

DAC Channel Name Gain Adjusted Diff (%) Phase (°) Delay (us)
0 H1:SUS-ETMX_L3_ESD_DC 1.00239 1.00114 0.11% -5.29955 -14.72
1 H1:SUS-ETMX_L3_ESD_UR 1.00026 0.99901 -0.10% -5.10734 -14.19
2 H1:SUS-ETMX_L3_ESD_LR 1.00000 0.99875 -0.12% -4.93122 -13.70
3 H1:SUS-ETMX_L3_ESD_UL 1.00103 0.99978 -0.02% -5.11118 -14.20
4 H1:SUS-ETMX_L3_ESD_LL 1.00088 0.99963 -0.04% -5.21524 -14.49
8 H1:SUS-ETMX_L1_COIL_UL 1.00400 1.00275 0.27% -4.72888 -13.14
9 H1:SUS-ETMX_L1_COIL_LL 1.00295 1.00170 0.17% -4.88883 -13.58
10 H1:SUS-ETMX_L1_COIL_UR 1.00125 1.00000 0.00% -5.08727 -14.13
11 H1:SUS-ETMX_L1_COIL_LR 1.00224 1.00099 0.10% -4.92882 -13.69
12 H1:SUS-ETMX_L2_COIL_UL 1.00325 1.00200 0.20% -4.78859 -13.30
13 H1:SUS-ETMX_L2_COIL_LL 1.00245 1.00120 0.12% -4.55283 -12.65
14 H1:SUS-ETMX_L2_COIL_UR 1.00175 1.00050 0.05% -4.52503 -12.57
15 H1:SUS-ETMX_L2_COIL_LR 1.00344 1.00219 0.22% -5.00466 -13.90
  Average 1.00199 1.00074 0.07% -4.93611 -13.71
  Standard Deviation 0.00125 0.00125 0.13% 0.23812 0.66
Comments related to this report
daniel.sigg@LIGO.ORG - 15:53, Thursday 12 September 2024 (80064)

FPGA filter is

zpk([585.714+i*32794.8;585.714-i*32794.8;1489.45+i*65519.1;1489.45-i*65519.1;3276.8+i*131031; \
    3276.8-i*131031;8738.13+i*261998;8738.13-i*261998], \
    [11555.6+i*17294.8;11555.6-i*17294.8;2061.54+i*26720.6;2061.54-i*26720.6;75000+i*93675; \
    75000-i*93675;150000+i*187350;150000-i*187350;40000],1,"n")

Non-image files attached to this comment
H1 General
ryan.crouch@LIGO.ORG - posted 16:00, Tuesday 10 September 2024 (80027)
OPS Tuesday EVE shift start

TITLE: 09/10 Eve Shift: 2330-0500 UTC (1630-2200 PST), all times posted in UTC
STATE of H1: Preventive Maintenance
OUTGOING OPERATOR: Ibrahim
CURRENT ENVIRONMENT:
    SEI_ENV state: CALM
    Wind: 19mph Gusts, 12mph 3min avg
    Primary useism: 0.02 μm/s
    Secondary useism: 0.10 μm/s
QUICK SUMMARY:

H1 TCS
camilla.compton@LIGO.ORG - posted 14:57, Tuesday 10 September 2024 - last comment - 14:26, Monday 11 November 2024(80025)
CO2s turned up from 1.7W to 2.0W for 7 minutes before lockloss

TJ and I turned up the CO2s from 1.7W to 2.0W today before we lost lock for Tuesday Maintenance at 2024/09/10 15:10 UTC. We then lost lock at 2024/09/10 15:18 UTC. We did this after mention that PRCL to CHARD coupling could be reduced by CO2 power changed in 79989, but we didn't have time to think about if we should make an injection.

Comments related to this report
camilla.compton@LIGO.ORG - 14:26, Monday 11 November 2024 (81201)SQZ

Checked when we turned the CO2s up for 7 minutes, that this had no noticeable effect on squeezing level or sqz alignment, plot attached. But maybe 7 minutes isn't long enough to see any changes, we could try again with more time or try turning the CO2s off before Tuesday Maintenance

Checking as LLO sees the Squeezing and SQZ alignment/mode matching  may be related to changes in CO2 power (or alignment), see 72244

Images attached to this comment
H1 SUS
ryan.crouch@LIGO.ORG - posted 14:28, Tuesday 10 September 2024 (80021)
Weekly In-lock charge measurement

Closes FAMIS 28370

All the measurements ran, ITMX could not be processed due to low bias_drive_bias_off coherence.

No clear trends, everything seems steady.

Images attached to this report
H1 AOS (ISC)
marc.pirello@LIGO.ORG - posted 13:19, Tuesday 10 September 2024 (80020)
SUSEX Ligo DAC 32 (LD32) testing at EX

Per WP12079 we started measurements to compare directly the 20 bit DAC driving the ESD and L3 to our LD32. 

Comparing ESD Driving Signals
Test 1 - LD32 bank 1 (ch 0-7) attached to 0-7 on the PEM ADC ; 20 bit DAC ESD signal attached to 8-15 on the PEM ADC

Comparing L3 Driving Signals
Test 2 - 20 bit DAC L3 attached to 0-7 PEM ADC : LD32 bank 2 (ch 8-15) attached to 8-15 on the PEM ADC

After analysis of the data, we measured about ~14us delay in the LD32 which is accounted for by the Anti Imaging filter on the FPGA.  We also determined the gain should be ~275.65 to achieve the same calibration between both DACs.

Driving the ESD and L3 with the LD32 will be postponed until next week.

daniel sigg, dave barker, marc pirello

H1 SQZ
camilla.compton@LIGO.ORG - posted 12:14, Tuesday 10 September 2024 - last comment - 19:33, Wednesday 11 September 2024(80010)
PSAMS adjustments for SQZ-OMC mode matching

Vicky, Camilla

Repeated 66946 PSAMs changes with SQZ-OMC scans with a new method of dithering the PZT around the TEM02 mode and minimizing it. With this we improved the mode mismatch from 4% to 3%. It will interesting to see if these settings are still better in full lock. Plots of OMC scan attached and same plot zoomed on peaks attached.

Took OMC scans using tempalte /sqz/h1/Templates/dtt/OMC_SCANS/Sept10_2024_PSAMS_OMC_scan_coldOM2.xml  Unlock OMC and H1:OMC-PZT2_OFFSET to -50 (nominal is-17) before starting scan.

Started with strategy 1: Lock OMC and Maximize TEM00 with PSAMS (alignment controlled with loops).
Changed to more sensitive strategy 2: Vicky put a dither on the OMC PZT around the TEM02 peak, awggui attached. Then minimize TEM02 peak with PSAMS (alignment controlled with loops).
 
ZM4/5 PSAMs TEM00 TEM02
Mismatch
(% of TEM02)
Notes Ref on Plot
5.5V/-0.8V 0.6362 0.02684 4.048% Starting 0 (pink)
4.0V/0.34V 0.6602 0.02332 3.412% Maximized TEM00 1 (blue)
2.1V/0.2V 0.6611

0.02097

3.074% Minimized TEM02 2 (green) This is 0V on the ZM4 PZT.
3.0V/0.85V 0.6609 0.02209 3.234% Minimized TEM02 3 (orange)
4.0V/0.34V N/A N/A N/A Minimized TEM02 Didn't scan, checked that we got similar results with different method of minimumizing TEM02 rather than maximizing TEM00
8.1V/-0.4V 0.6422 0.03432 5.073%
Minimized TEM02
4 (cyan)
Chose similar ZM4 settings to  what we found was good in full lock with cold OM2 in 76986

2.1V/-0.1V

0.6591 0.02162 3.176% Minimized TEM02 5 (red)

2.1V/0.2V

0.6580 0.01954 2.884% Back to best ref2 PSAMS values 6 (brown) LEAVING HERE

Over 1V and under -1V on ZM5 is bad at most ZM4 strains (tested at 4.0V ZM4). For each step we adjusted ZM4 and then fine adjusted ZM5.

Images attached to this report
Comments related to this report
victoriaa.xu@LIGO.ORG - 14:58, Tuesday 10 September 2024 (80024)ISC, SQZ

Note OM2 is cold currently for this measurement (and since the vent it seems).

Images attached to this comment
camilla.compton@LIGO.ORG - 11:55, Wednesday 11 September 2024 (80045)

With the orginal PSAMs (5.5V/-0.8V) we had:

  • OMC locked 1-2 min, starting from 1410019031.
    • TRANS, DCPD_SUM_OUT = 0.65.
    • REFL, OMC-REFL_A_LF_OUT between (0.06,0.18)
  • OMC unlocked 30s, starting from 1410019336.
    • TRANS DCPD_SUM_OUT = 0.009.
    • OMC-REFL_A_LF_OUT between (0.86,0.99)

At the better PSAMS settings (2.1V/0.2V) plot attached:

  • OMC locked 1-2 min, starting from 1410027768.
    • TRANS DCPD_SUM_OUT = 0.67
    • OMC-REFL_A_LF_OUT between (0.036, 0.167)
  • OMC unlocked 1 min, starting from 1410028000.
    • TRANS DCPD_SUM_OUT = 0.0087
    • OMC-REFL_A_LF_OUT between (1.008, 0.87)
  • DARK OMC 1 min, starting from 1410028321.
    • TRANS DCPD_SUM_OUT = 0.0084
    • OMC-REFL_A_LF_OUT between (-0.02, -0.01)
Images attached to this comment
H1 CAL
louis.dartez@LIGO.ORG - posted 11:28, Tuesday 10 September 2024 - last comment - 14:05, Tuesday 10 September 2024(80017)
ETMX L1, L2, L3 COILOUTF and ESDOUTF gain adjustments for new 32-bit DACs
In preparation for WP 12079, I prepared ESDOUTF (L3) and COILOUTF (L1, L2) filters to make up the calibration difference between 18-bit and the new 32-bit DACs. This is similar to what was done in LHO:64274 to adjust from 18-bit DACs to 20-bit DACs. Similarly, I placed new '32bitDAC' gains in CALCS-ETMX. In CAL-CS, the new gains are intended to replace the gains of '4'. 

I have not yet loaded the filter coefficients, but they have been saved in the filter files. 
Comments related to this report
jenne.driggers@LIGO.ORG - 14:05, Tuesday 10 September 2024 (80022)

I loaded the filters earlier today, so they should be ready to go whenever we start using these new LIGODACs in-loop.

H1 ISC
elenna.capote@LIGO.ORG - posted 16:47, Thursday 05 September 2024 - last comment - 16:33, Tuesday 10 September 2024(79939)
DARM comparison, BRUCO results post-commissioning

We made some improvements today in the sensitivity, going from about 151 Mpc on GDS CLEAN to about 158 Mpc. However, our best range from April 11th (DARM FOM reference pre-OFI disaster) is around 165 Mpc. I made a comparison of that time and now with today's commissioning improvements to see where we are still missing range. I have attached the four plot results from the darm_integral_compare results (see alog 76935 for directions).

The range integrand plot makes it much easier to see that we are still missing sensitivity around the mid-frequency band. However, the sensitivity difference shows that we lose 5 Mpc of range by 40 Hz as well. Much of this range loss seems to come from a variety of peaks that have appeared since the OFI vent, such as the 20 Hz peak. We lose another ~3 Mpc between 40-200 Hz.

I ran a bruco with GDS CALIB STRAIN CLEAN on high range time after commissioning today: post-commissioning bruco

It looks like many of these new low frequency peaks (like the large 20 Hz peak) are well witnessed by things like PSL accelerometers, indicating that they could be from jitter: PEM-CS_ACC_PSL_TABLE1_Y_DQ

Generally, there is a lot of jitter coherence, and given that this is the CLEAN channel, that's probably a sign that the jitter cleaning could be improved, maybe making use of other witness channels if the current witnesses are insufficient to subtract the noise.

A peak at 30 Hz has some coherence with MAG sensor channels, here is one: PEM-CS_MAG_LVEA_VERTEX_X_DQ

Right around 35.4 Hz, there is a lot of coherence with various ISI HAM6 sensors and OMC ASC sensors. For example: ISI-HAM6_GS13INF_V1_IN1_DQ

There is also still a large amount of LSC REFL RIN coherence up to 1 kHz: LSC-REFL_RIN_DQ

I think we should test the PRCL offset again, especially because this will help reduce the CHARD Y noise coupling (ASC-CHARD_Y_OUT_DQ) and will also possibly help this HF noise (frequency noise? intensity noise?)

SRCL is better than before, but maybe has more room for improvement between 10-25 Hz: LSC-SRCL_OUT_DQ

DHARD Y coherence is low, but still present, so we should be careful with the WFS offset: ASC-DHARD_Y_OUT_DQ

There is still PRCL coherence: LSC-PRCL_OUT_DQ which is likely coupling through a combination of CHARD Y, SRCL, and LSC REFL RIN. Again a PRCL offset will help. Other strategies are to check POP phasing, POP sensing, etc. Reminder: PRCL feedforward failed, so we need to consider other avenues for noise reduction.

To summarize some strategies to get back to April sensitivity:

Editing because I went back to check the previous PRCL offset work and found this comment: 76818, in short, we can fix the REFL RIN coherence, but it has no effect on the sensitivity. However, it can improve CHARD Y noise, although at the time I don't think we were limited by CHARD Y enough to see the low frequency benefit.

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Comments related to this report
derek.davis@LIGO.ORG - 11:29, Friday 06 September 2024 (79948)DetChar, DetChar-Request

Regarding the 20 Hz line, this line disappeared from DARM yesterday (Sept 5) from roughly 12:45 - 14:15 UTC. Matching Elenna's note about coherence with PSL environmental channels, the same line disappears from the PSL microphones and accelerometers at the same time. Furthermore, there are short time windows where this line dissapears from PSL channels. This behavoir happens roughly (not the exact same gap each time) at 2 hour intervals.

These clues may be helpful for any investigation into the source of this line.  

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elenna.capote@LIGO.ORG - 15:18, Friday 06 September 2024 (79953)

Another note about PRCL Offsets and CHARD Y:

I have attached a screenshot plot comparing the PRCL offset on/off times with the noise in CHARD Y (I used the on/off times from this April alog: 76814). The PRCL offset did reduce the noise in CHARD Y a small amount, and also reduced the CHARD Y coherence with DARM. I don't think at the time of this test we were limited by CHARD Y, so we didn't actually see a change in sensitivity from this test. Therefore, it's worth trying the offset again since we seem to have more CHARD Y noise coupling right now.

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elenna.capote@LIGO.ORG - 16:33, Tuesday 10 September 2024 (80029)

Here is a comparison of a longer-span time from April and from last night's lock. Using 2 hour blocks of no-glitch time I created these darm comparison plots.

There were further small improvements in the sensitivity from when these plots were last made, so they are not completely comparable to the plots in the original alog.

These plots indicate that we have actually gained some low frequency sensitivity since April, although we are definitely seeing more peaks around low frequency than before the emergency vent. We are still missing some range around 100 Hz.

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