J. Kissel, P. Fritschel

We've since measured the noise in the lowest noise modes,
UIM: with all low-pass (LP) filters ON (i.e. setting the UIM BIO State Request to 4.0)
PUM: with acquire (Acq) bit OFF and and low-pass (LP) ON (i.e. setting the PUM BIO State Request to 3.0)
(with both COIL/TEST Enable bits set to 1.0)

and the results are more like what's expected from the design studies

     (Measured Output Referred Noise)
     (      Lowest Noise Mode       )
     (    [V_out/rtHz] @ 10 Hz      )

UIM:             ~1.5e-8 

PUM:             ~1.5e-8 


Unlike the earlier measured noise, the input DAC noise is filtered down by some factors, so the "component noise," the self-noise of the resistors, op-amps, etc. is "exposed." 
- For the UIM, the input/DAC noise is squashed by 3 10Hz low pass filters, so the dominant noise is the coil-driver, component self noise at all frequencies (above 10 Hz). One can just barely see a little bump creeping in around 300 Hz from the DAC noise, which is from the [z:p]=[60:325] frequency response inherent to the output stage.
- For the PUM, the DAC noise is only filtered out in the region around 10-20 Hz (in the "tough" region where the SUS noise is potentially dominant in the DARM spectra), but otherwise rolls back up according to the [z:p] = [13:130] frequency response inherent to the output stage (with the Acq bit OFF), so at high frequency the output noise re-asymptotes to 100 [nV/rtHz].

A couple of other things to notice when comparing the above data with this data:
- In the UIM driver, whose output noise is dominated by DAC noise in Acq mode, and Component Noise in Low Noise mode, one can clearly see 60Hz lines in the Component Noise.
- The spikes in the PUM output noise have shifted in frequency, and are not 60 Hz lines... not sure what that means or why.

This data can be found committed to the SusSVN repository here:

/ligo/svncommon/SusSVN/sus/trunk/QUAD/H2/ETMY/Common/Data/
2012-06-12_H2SUSETMY_L1L2_NoiseMon.pdf [first attachment]
2012-06-12_H2SUSETMY_L1L2_NoiseMon.xml [first measurement]
2012-06-12_H2SUSETMY_L1L2_NoiseMon_LowestNoiseModes.pdf [second attachment]
2012-06-12_H2SUSETMY_L1L2_NoiseMon_LowestNoiseModes.xml [second measurement]

where the "*LowestNoiseModes.xml" has the first measurement as references.

J. Kissel

Another measurement for these two driver to facilitate on-going electronics studies: leaving both drivers in low noise mode (UIM: LP1, LP2, LP3 all ON; PUM: Acq OFF, LP ON), but switching between the COIL In (connected to the AI/DAC) and TEST In (assumed to be an open DB9 connector).

Attached are the results. You'll notice that there are is no change in the noise floor between the two states on the UIM driver, but for the PUM the four channels get totally different noise (from the COIL In state, and from each other).

What did we expect? It's a long story (eventually, the story will be told in L1200193), but in short:
- Each coil driver board (yes, all of them) has a equi-potential voltage reference plane to which on-board components are grounded (called "0V" on the schematic). 
- The given coil driver chassis forms a second equi-potential plane (which we'll call "ground" for now)
- The "0V" reference plane is connected internally to pin 5 of both the "COIL In" and "TEST In" DB9 connections (called "DEMANDS" and "Front Panel Test Inputs" on the schematics), as well as to several of the output pins.
- External to the chassis, the system wiring diagrams (yes, all of them) show that all of these pins are shown to be "NC" or "not connected" to cables going to and from these chassis.
- It's unclear *how* they are not connected: is the pin is shorted to the chassis, to the backshell, or maybe the cable doesn't have a pin in it's female socket ... could be any number of things.
- In the as-measured configuration of the electronics, the "COIL In" DB9 is connected to the full signal chain as shown in the system wiring diagram (D1002741); the "TEST In" DB9 is open to air (and not shown in D1002741).
- In general, the chassis "ground" is free to swing with the surrounding environment, whose changing electric field can then interact with the reference ground "0V" on the boards, and also interact with the the components on the board.
- IF and ONLY IF the differential paths are identical (which, in the real world is not possible because of component tolerances), this changing field would be common-mode to the two positive and negative paths, and cancel. 
- However, IF the paths are not perfectly the same, the common-mode surrounding field will couple differentially to the components and cause noise for various reasons.

The HOPE was that there was no such coupling between the "0V" reference plane and the "ground" plane of the chassis going on, the switch between "COIL In" and "TEST In" would merely remove the (filtered) 100 [nV/rtHz] Input DAC noise, and we could therefore measure the component, self-noise of the board at the output.

For the UIM board, the noise level remained roughly the same. We expected the noise in the "COIL In" configuration to be dominated by the component noise, so if we've "turned off" the DAC noise by switching to the TEST In configuration, we indeed expect no change. GOOD!
For the PUM board, the DAC noise was not filtered as much as the UIM board in the lowest noise mode and is therefore dominant, so we expected to see the noise on all channels to simultaneously drop to the component, self-noise noise level when switching to "TEST In." Instead we see what's shown -- each channels noise is differently elevated, and its frequency response has changed.

I don't want to make claims just yet of exactly what's happening (which is why I said "for various reasons), but the proposal L1200193 will suggest what to do next.

Weeeeeee-ew. How do you say ... l'enquête se poursuit!