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Reports until 10:55, Wednesday 25 February 2026
H1 SPI (CDS, SEI, SPI)
jeffrey.kissel@LIGO.ORG - posted 10:55, Wednesday 25 February 2026 (89263)
SPI Single-element Photodiode Short Check :: No Shorts Pin-to-Pin -- Everything Good-to-GO
J. Freed, J. Kissel

We worried for the production, already class-A clean, SPI's single-element PD (SPD) assembly (D2600001) that the unused GAP5000 pins of the dual-purpose D1700116 ceramic circuit board may have shorts from FFD-200 SPD case to its anode and cathode if the case of the PD was not insulated from those GAP5000 pins -- as was found possible in the dirty test setup (see list item 2. in LHO:89247).

This morning, we opened up the cleaned assemblies (still serialized under the drawing for the cable, D2400341),
    - S2500514 :: HAM3 ISIK MEAS A and MEAS B
         --Pins 5-9 -> PD Box S2400197 -> DCPD 001
         --Pins 4-8 -> PD Box S2400198 -> DCPD 002
    - S2500515 :: HAM3 ISIK FBR PWR REF and FBR PWR MEAS
         --Pins 5-9 -> PD Box S2401094 -> DCPD 004
         --Pins 4-8 -> PD Box S2401093 -> DCPD 003
    - S2500516 :: HAM3 ISIK REF A and REF B
         --Pins 5-9 -> PD Box S2401096 -> DCPD 005
         --Pins 4-8 -> PD Box S2401095 -> DCPD 006

And found that for every assembly,
    - Per D2400341, only pins 1,4,5,8, and 9 exist. See example picture of S2500514
    - All the anode (5 or 4) or cathode (9 or 8) pins are isolated from the case pin (Pin 1)
    - The anode pins for the two diodes (5 and 4) are isolated from each other
    - The cathode pins for the two diodes (9 and 8) are isolated from each other
    - Each diode's cathode to anode resistance (5 to 9 and 4 to 8) is in the ~2e6+/-1 [Ohm] = ~few [MOhm] as expected for the reverse bias operation we'll use the system.

The production PD assembly will function as designed without any shorts :: the negative reverse bias topology of the transimpedance amplifier and cable readout system will work!

I also attach pictures of the bags that aide assignment of serial numbers to assemblies.

Images attached to this report
H1 ISC (CDS, ISC)
keita.kawabe@LIGO.ORG - posted 14:58, Tuesday 24 February 2026 - last comment - 15:21, Tuesday 24 February 2026(89244)
ASC QPD (not WFS) whitening gain were somehow set to zero

It seems that whitening gains of some corner station QPDs were somehow set to zero on Friday Feb/20 17:22 UTC (09:22 PST).

Not sure why this happened, this seems to be earlier than the failed effort to update h1imcasc model (alog 89208). ALS QPDs, end station QPDs and all WFS RFs are good. Was something done to Beckhoff that day? 

I first noticed this for MC2 trans yesterday because it was interfering with IMC locking and WFS triggering. I checked all QPDs and WFS today and found that the following channels were affected. I restored them all to the value right before it was set to zero. 

channel old (dB) new (dB)
H1:IMC-MC2_TRANS_WHITEN_GAIN 0 30
H1:IMC-IM4_TRANS_WHITEN_GAIN 0 18
H1:ASC-AS_C_WHITEN_GAIN 0 18
H1:ASC-OMC_A_WHITEN_GAIN 0 27
H1:ASC-OMC_B_WHITEN_GAIN 0 27

 

Images attached to this report
Comments related to this report
ryan.short@LIGO.ORG - 15:21, Tuesday 24 February 2026 (89245)

Trending the uptime of the Ethercat system, slow controls were restarted and came back up two seconds before the time listed in Keita's alog, likely a part of Daniel's updates to include CHETAX electronics (alog89211). Settings may just have not been fully recovered after that restart.

H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 16:42, Thursday 19 February 2026 (89198)
PM1, RM1, RM2, JM1, JM3 COILOUT/DAMP filters updated to solve our confusion

Rahul, Jeff, Oli

In December 2025 when we needed to compensate for the HAM1 DACs moving from 16- to 28-bit, we had decided to have FM10 in the COILOUTF bank be gain(1024), and put the remaining gain(4) upstream in multiple other places (88553). This led to our confusion today when we realized that when taking transfer functions for PM1 and JM3, the TEST banks had gone back to gains of 1 a couple weeks ago, and since we had damping off, the extra gain wasn't going through to the excitation. This might at least partially be why PM1 had dropped in magnitude, and why the JMs are so low in magnitude too.

To solve confusion, I've gone through PM1, RM1, RM2, JM1, and JM3 and removed the extra gain(4) that's in:
- DAMP bank FM4
- TEST bank gains (if still there)
- OPTICALIGN gains
- LOCK filter bank gains
Then I updated the gains in COILOUTF FM10 from gain(1024) to gain(4096).

I've sdf'd the values and loaded in the changed filter modules. I also committed the filter file.

*To remove future confusion about the difference in value of the "28BitDAC" filter module in COILOUTF FM10, I am going to go through all the suspensions and change the name of that filter from "28BitDAC" to be something like "16to28Bit" or "18to28Bit" depending on the previously used DAC bits

H1 IOO (CDS, IOO, ISC)
keita.kawabe@LIGO.ORG - posted 14:15, Wednesday 18 February 2026 (89183)
IMC ASC model needs a better JAC integration

Or, rather, a better JM3 integration and PSL unintegration.

I made a temporary IMC_WFS_MASTER and IMC_WFS_OUTMATRIX_kk screen such that it's easy to route IMC WFS signal to JM3, not the PSL PZT, because I wanted something that works now.

However, right after I made what looks to be an OK screen, I realized that this doesn't work. PIT signal should be routed to JM3 YAW and vice versa. No fully-working IMC WFS until the next model update.

In addition, earlier today Daniel suggested to nuke PSL PZT from the IMC ASC (good idea).

If you want to revert back to the old medm, copy the backup

/opt/rtcds/userapps/trunk/asc/common/medm/imc/IMC_WFS_MASTER_BAK_20260218.adl 

to

/opt/rtcds/userapps/trunk/asc/common/medm/imc/IMC_WFS_MASTER.adl 

Images attached to this report
H1 SQZ (CDS)
camilla.compton@LIGO.ORG - posted 12:52, Thursday 05 February 2026 (89048)
HAM7 Ground Loop Checks

Sheila and I followed T2200048 to check for ground loops in the SQZ rack yesterday while the HAM7 door was being put back on. Did not check picos. Results attached.

Strange ones noted below: 

Non-image files attached to this report
H1 General (CDS, OpsInfo, SEI, SUS)
anthony.sanchez@LIGO.ORG - posted 17:17, Monday 02 February 2026 (88997)
Monday Ops Day of Mysteries

TITLE: 02/03 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY:
LVEA was Bifircated via a Laser Hazard areas around HAM 1& 2, while the rest of the LVEA is LASER SAFE unless at height. See M2600004 for details.

PM1 was mysteriously dancing & Saturating too much for Rahul's transfer function measurement all day long. While he was troubleshooting. Update!!! Rahul dragged the EE guys out and found a dead Coil Driver! Mystery solved!

JAC work continued all day starting with mode matching in HAM1, and starting a JM2 swap. JAC table now has all the mounts and Cables but no optics yet. 

HAM7 & ITMY ISI Watchdogs tripped at 23:33 UTC due to mysterious high frequency ground noise that was louder at HAM7 than ITMY.  Jim & Betsy went to go look for fallen wrenches or other watchdog tripping phenomena..... No explanation was ever found. 

OPS info: 
New conda ENV doesn't run watchdog untripping scripts unless you run Conda Kill first.  Tagging CDS. 

LOG:

Start Time System Name Location Lazer_Haz Task Time End
22:49 SAF LVEA IS LASER SAFE LVEA NO* LVEA IS LASER SAFE *BIFURCATED HAM1/2 bring ur LASER GOGGLES 16:49
15:35 FAC Nellie Optics Lab n Tecnical cleaning 15:55
15:37 JAK Betsy LVEA y checking status of LVEA 16:37
15:44 FAC Kim LVEA y technical cleaning 17:55
16:50 SAFETY Travis LVEA yes Setting up barriers for Bifurcated laser hazard  conditions. 17:26
16:56 Cheta Camilla, Matt, Sophie CHETA  lab Yes Updating Camilla on CHETA lab status 18:55
17:06 FAC Nellie LVEA y Technical Cleaning 17:55
17:16 Cheta Ryan CHETA Lab y Getting Optics 17:23
17:21 PSL Jason LVEA yes Energizing the rotation stage to 1 W. 17:30
17:22 Safety Jenny D LVEA y Setting up barriers for Bifurcated Laser zones. 17:26
17:26 SUS Rahul Remote n Taking TF meas. of PM1 18:26
17:28 VAC Travis LVEA y Reducing purge air in HAM1 17:30
17:35 SPI Jeff Optics lab Yes Working on SPI in the Optics Lab. 20:34
17:57 CHETA Ryan S CHETA LAB y Getting optics parts 18:12
18:06 FAC Kim Mid X n technical cleaning 18:54
18:09 SEI Jim LVEA HAM7 n Balancing HAM7 ISI 19:19
18:15 SEI Mitchel LVEA HAM78 N Balancing HAM7 19:19
18:28 VAC Travis LVEA HAM1 y Turning up purge air 18:33
18:30 SUS Rahul LVEA & Optics lab y getting & cleaning parts 18:55
18:31 Laser Trans Oli LVEA Y Laser transitioning to Strange Laser Bifurcated State 18:41
18:34 SQZ Sheila & Karmeng SQZr Racks n Checking on SQZr racks 21:31
18:45 JAC Masayuki & Jason LVEA HAM1 YES JAC Mode matching 20:19
18:48 JAC Ryan S LVEA HAM1 YES Taking picures of JAC & pluggin in the JAC Table. 19:06
18:55 FAC Kim HAM SHAQ N Technical Cleaning 20:25
19:12 TCS Matt OptLab y(local) Putting stuff away 19:18
19:45 VAC Gerado LVEA yes/no Anulus pump work 20:24
19:47 ISC Mitchel LVEA West bay n Getting parts. 20:07
20:09 JAC Jennie LVEA HAM1 YES Checking on Jason and Masayuki 20:19
20:49 LASER SAFETY Travis LVEA HAM1 YES Adjusting the LASER Curtain. 21:03
20:55 FAC Randy LVEA n heading to the WEST Bay area for parts. 22:20
20:56 JAC Betsy Optics Lab y Checking for parts and progress. 22:56
21:01 SPI Jeff & Jim Optics lab Yes Working on SPI 23:01
21:11 EE Marc LVEA HAM1 yes Working with the HAM1 crew 22:56
21:21 JAC Ryan S LVEA JAC Table N working on the JAC table 01:51
21:27 VAC Travis LVEA HAM1 yes Adjusting the Purge air back down for a SUS measuremnent 22:29
21:28 SUS Rahul Remote. N JAC PM1  SUS TF Measurement 22:13
21:36 JAC Jennie W LVEA JACt & HAM1 n/Y working with Ryan S on JAC table, & Waiting for HAM1 crew. 00:00
21:37 SUS Rahul LVEA HAM1 Y Checking PM1 SUS  status 22:12
21:58 FAC Mitchel LVEA West bay N Checking inventory & Parts 22:35
22:05 JAC Betsy LVEA N Running parts 23:59
22:23 JAC Masiuki & Jason LVEA HAM1 Yes Working on Mode matching with JAC 01:58
22:31 JAC Keita LVEA HAM1 Yes Helping HAM1 crew 01:56
22:34 VAC Travis LVEA HAM1 Turning up the Purg air in HAM1 22:43
23:00 JAC Betsy LVEA yes Running parts 23:30
23:39 VAC Travis HAM Shaq N Getting parts. 23:45
23:54 CHETA Camilla Optics Lab N Checking supplies. 00:00
00:06 SUS Rahul LVEA yes Power cycling Satilite boxes 00:10
00:06 SEI Jim LVEA N Walking through the LVEA looking for fallen wrenches & unwatched dogs 00:46
00:10 SEI Betsy LVEA yes Walking around looking Unwatched Dogs 00:30
00:18 SUS Fil & Rahul LVEA HAM1 yea power cycling sat amps to troubleshoot SUS OSC rahul out early 00:57
00:28 EE Marc LVEA HAM1 yes Giving Fill a hand 00:57

 

Images attached to this report
H1 ISC (ISC)
keita.kawabe@LIGO.ORG - posted 14:30, Monday 02 February 2026 - last comment - 18:24, Monday 02 February 2026(88994)
Modulation index measurements (JennieW, Masayuki, Jason, Elenna, Daniel, Keita)

Used 1W into JAC.

9 (26.8dBm into EOM), 45 (27dBm) and 118MHz (10.76dBm) -> Used a single bounce beam from ITMX and scanned OMC. Successful for 9 and 45, nothing visible for 118. Detailed will be posted later.

24MHz (IMC, 14.2dBm) -> Scanned IMC length and tried to find something in IMC transmission. Nothing visible.

43MHz (JAC, 12.2dBm) -> Scanned JAC, saw nothing in JAC transmission. Boosted RF  power with an amp to 29.67dBm -> m=0.092. Without the amp modulation index would be 0.012.

9MHz 26.5/26.8dBm (readback/requested) 0.26
45 27/26.7 (readback/requested)

0.31

118 10.76 Not measured yet
24 (IMC) 14.2 Not measured yet
43MHz (JAC) 12.2 (temporarily boosted to 29.67 for measurement) 0.012 (w/o boosting the RF level)

 

Comments related to this report
jennifer.wright@LIGO.ORG - 17:40, Monday 02 February 2026 (89003)

Mode scans saved as /ligo/home/jennifer.wright/git/2026/JAC/20260202_OMC_scan.xml

keita.kawabe@LIGO.ORG - 18:11, Monday 02 February 2026 (89004)

43MHz details.

We temporarily boosted RF level into EOM in the PSL room to  29.67dBm, scanned JAC and measured the transmission.

43MHz 00 transmission = 0.0057.

C00 transmission (closest to 43MHz 00 mode )= 2.72.

m(29.67dBm) ~ 2*sqrt(0.0057/2.72) = 0.092.

Non-boost RF power =  12.2dBm

m(12.2dBm) = m(29.67dBm) * 10^((-29.67+12.2)/20) = 0.012.

Images attached to this comment
keita.kawabe@LIGO.ORG - 18:24, Monday 02 February 2026 (89006)CDS, ISC

JAC PZT whitening cable and JAC TRANS PD whitening are cross-wired.

We were scratching our collective head that changing whitening gain and filter for JAC TRANS PD didn't do anything. Daniel checked the cabling and it was good. After a while it was found that maxing out the TRANS PD whitening gain changes the PZT voltage readback by about 30mV. Turns out that the PZT whitening and the TRANS PD whitening are cross-wired.

As an example, attached shows what you should do to set the whitening gain of the JAC TRANS PD to +3dB with one whitening filter ON. (Note that the digital filter is not cross-wired.)

Images attached to this comment
jennifer.wright@LIGO.ORG - 17:38, Monday 02 February 2026 (89001)

This morning Masayuki and Keita turned the 9 and 45 MHz RF supplies in the PSL rack up to  26.5dBm and 26.8dBm, respectively.

We took another mode scan with the IMC using the template at userapps/omc/h1/templates/OMC_scan_single_bounce_slower.xml.

We can now measure the 9 and 45 MHz sidebands.

Pink is Friday's measaurement with the RF power for 9 and 45 turned down, yellow is today.

The cursors are at the carrier and 9 MHz peaks in this image and the carrier and 45 peaks in this image.

This makes m_45 = 0.31 and m_9 = 0.26, for the modulation index of 45 MHz and 9MHz sidebands respectively.

The 118 Hz peak was buried in the noise, looking back at this measurement from Elenna in alog #62730, the 118 MHz  only shows up as a peak below 0.002 mA, so it would be hard to see with our current power, maybe possible if we went up to 10 W (factor of ~ in amplitude).

Images attached to this comment
H1 CDS (CDS)
erik.vonreis@LIGO.ORG - posted 06:51, Tuesday 27 January 2026 (88903)
Workstations updated

Workstations were updated and rebooted.  This was an OS packages update.  Conda packages were not updated.

H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 17:42, Thursday 22 January 2026 (88861)
Summary of Conversion from SUSB123 & SUSH34 to SUSB13 & SUSB2H34 ('No QOSEMs/BBSS' Configuration)

Here is the summary with all the relavant alogs for the conversion from SUSB123 and SUSH34 to SUSB13 and SUSB2H34*.

*Our current configuration, specifically for SUSB2H34, is an interim state ("No QOSEMs/BBSS" config) on the way to the final O5 configuration, so SUSB2H34 doesn't fully match the cabling diagrams seen in D2300383. We can't fully upgrade to this O5 version yet because we don't have the BBSS, LO1, or LO2 installed yet, and need to be able to actuate the BSFM for the February commissioning period. To see what still needs to be done to get from this interim period to the final O5 configuration, see 88860 and google slides.

SUSB13 wiring diagram: D2300401
SUSB2H34 wiring diagram: D2300383

CER hardware changes88765
    AI chassis upgrades: 88766
    New power rail in SUS-C1: 88850
    Fix for failed untouched chassis: 88849
    BIO cable naming convention: 88852
    Renaming of SR3 OPLEV cable: 88837
    Updated SUS-C1/C2/C5/C6 rack photos: 88848
    Current status of SUS-C1/C2 racks vs Final O5 build: 88860
SUS Model Updates:
    ITMX: 88812
    ITMY: 88813
    ITMPI: 88818
    BS: 88814
    MC2: 88815
    PR2: 88816
    SR2: 88817
    AUXB123 -> AUXB13: 88819
    AUXH34 -> AUXB2H34: 88820
SUS Model Installation: 88781

H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 17:34, Thursday 22 January 2026 - last comment - 09:21, Tuesday 27 January 2026(88860)
Current Status of SUS-C1/C2 Racks vs Final O5 Build

J. Kissel, O. Patane, D. Barker, F. Clara, M. Pirello

Our big SUSB123 and SUSH34 to SUSB13 and SUSB2H34 upgrade last week wasn't the full upgrade for O5.
SUSB13 is fully upgraded to its O5 configuration, but for SUSB2H34, we can't fully upgrade to the final O5 build yet because we still need full control of the BSFM for the February commissioning period, whereas O5 will have the BSFM replaced with the BBSS (with QOSEMs instead of BOSEMs), requiring different electronics. The final O5 build will also include the electronics for the new suspensions LO1 and LO2. Going from the current configuration, which we call the "No QOSEMs/BBSS" configuration, to our final O5 build will require eight new chassis and two new ADC cards.

Since we will be needing to add/change things on the racks, that future upgrade will also come with user model additions/changes.

Table showing comparison diagrams

  Current “No QOSEMs/BBSS” Config Final O5 Config
Rack overviews slide31 slide33
DACs slide10 (excluding BS BOT/LO1/LO2 and AI in U13) slide10 (everything)
ADCs slide15 slide16
BIOs slide21 (excluding BS BOT chans) slide21 (everything)
AUX ADCs slide26 (excluding pink) slide26 (everything)

I've also attached the slides above in pdf form here. The full slides outlining all the changes O4 -> now -> O5 can be found here.

Changes needed to go from current configuration to final O5 configuration:
SUS-C1
    U33:: Remove cable inputs for (BSFM) BS M1 OSEM sensors, re-arrange cable inputs for BS M3 Oplev to make room for (BBSS) BS M3 OSEM sensors, and bring in PR3 M3 Oplev because we can
    U14:: Add (BBSS) BS M3 input for Binary Output
    U13:: Add (BBSS) BS M3 input for Binary Input
    U5 :: New D090006 TACQ Driver for (BBSS) BS M3

SUS-C2
    U22:: Add (BBSS) BS M3 Noisemon and (BBSS) BS M3 SFVmon inputs
    U20:: New D0902783 AA Chassis for LO1 M1 and LO2 M1 HAM-A Coil Driver Volt Monitors
    U16:: New D1300282 AA Chassis for (BBSS) BS M1 QOSEM sensors and LO1 M1 and LO2 M1 OSEM sensors
    U14:: Add (BBSS) BS M3 input to AI chassis
    U13:: New D2500353 AI Chassis for LO1 and LO2 Coil Actuation
    U9 :: New D1100687-v1 (100 Ohm Output Impedance) HAMA Coil Driver for LO1 M1 F1F2F3SD
    U8 :: New D1100687-v1 (100 Ohm Output Impedance) HAMA Coil Driver for LO1 M1 LFRTxxxx
    U6 :: New D1100687-v1 (100 Ohm Output Impedance) HAMA Coil Driver for LO2 M1 F1F2F3SD
    U5 :: New D1100687-v1 (100 Ohm Output Impedance) HAMA Coil Driver for LO1 M1 LFRTxxxx
    
susb2h34 IO Chassis
    Needs an additional ADC Card (and adapter card and internal SCSI cable)

susauxb2h34 IO Chassis
    Needs an additional ADC Card (and adapter card and internal SCSI Cable)

Images attached to this report
Non-image files attached to this report
Comments related to this report
oli.patane@LIGO.ORG - 09:21, Tuesday 27 January 2026 (88908)

To clarify a bit on the status of SUSB13 and SUSB2H34, "as of these Jan 2026 changes, the SUSB13 racks and IO chassis are 'fully upgraded,’ as only the ITM QUADs are left in this system and there are no changes to the QUAD control system electronics for O5, and we’ve now upgraded the whole chassis to use 28-bit 32CH LIGO DACs. For the SUSB2H34 racks and IO chassis, while we’ve imported the existing BSFM beam splitter control system electronics, that’s all we can do at this point and we need the BS under control as it was for the Feb 2026 commissioning period. After that’s done, and as the suspensions get installed, we’ll add electronics to upgrade the BSFM BS to become a BBSS BS (with M1 QOSEMs replacing the M1 BOSEMs, and new M3 OSEMs for sensing and control there), and we install the LO1 and LO2 HRTS electronics for BHD as needed. So, it may be a while before the wiring diagrams match reality again".

(Thanks to Jeff for the clearer wording!)

H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 17:24, Thursday 22 January 2026 (88819)
SUS Model Updates: h1susauxb13

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSB123 into SUSB13 for SUSAUXB13, we referenced slides 23 and 24. These changes were svn'd as r34396 and were installed and started last week (88781).

These are the changes we had to made for h1susauxb13 (previously called h1susauxb123):

CDS Parameter Block:
- Changed hostname from h1susauxb123 to h1susauxb13
- Removed specific_cpu

Input (before, after):
- Removed BS block
- Removed ADC6 and ADC7
- ADC0 flag going into ITMY block is now in ADC5
- ADC7 flag going into ITMY block is now in ADC0

ITMY block (before, after):
- Removed ADC7
- Everything that was previously ADC0 is now in ADC5
- Everything that was previously ADC7 is now in ADC0

Images attached to this report
Non-image files attached to this report
H1 SUS (CDS)
jeffrey.kissel@LIGO.ORG - posted 13:21, Thursday 22 January 2026 (88852)
Cable Label Convention for SUS BIO Cables; Re-labeled susb13's cables and Labeled susb2h34's cables
J. Kissel, O. Patane

In support of last week's CER / Electronics / Rack changes to move the Beam Splitter electronics over from the susb123 / SUS-C5 & C6 system to become a part of the expanded susb2h34 / SUS-C1 & C2 system (LHO:88765) we were re-mapping the beam splitters Binary IO Card system from the former susb123 to the new susb2h34 system.

In the susb123 system, the Beam Splitter shared it's BIO system with the ITMs' TST/L3 stage ESD Drivers. That meant that we couldn't migrate the electronics and cards to susb2h34 like the other parts of the beam splitter control system. So, a new BI and BO chassis were installed in SUS-C1, and a new BIO card was installed into the susb2h34 IO chassis. The 2x PCB100WS (HDRA100 to 2xD37 pigtail) cables that connect to/from the BIO card from/to the BI and BO chassis were also new.

However, the SUS wiring diagrams have never really depicted these BIO cables well, and thus didn't establish a cable naming convention. Worse, even though the PCB100WS pigtail cables connect into different places with different orientations w.r.t. the BIO card (which has two HDRA100 100-pin outputs), the cables themselves are identical. Further, the BIO card ends are in one rack (with the IO chassis) and the BI / BO chassis ends are in an (adjacent, but) different rack. These facts makes it really tough to follow or connect new additions if the existing system is poorly labeled and there's no written-down convention established.

Thankfully, there were hints of a convention on a few cables of the susb123 system, namely 
    SUS_${BI/BO_DestinationRack}_${BI/BO_DestinationUHieght}_${OUT/IN}
BUT -- 
    (1) The labels that were there only labeled one of the two pigtails so which was "CNA" connecting to the Lower 32 Bit BO/BI chassis input and which was"CNB" connecting to the Upper 32 Bits was very unclear, and 
    (2) at some point in their history the BI/BO destination u-heights for the BIO0 and BIO2 cards were flip-flopped.

So, I improved the convention to include the _CNA and _CNB, such that the cable naming convention is now 
    SUS_${BI/BO_DestinationRack}_${BI/BO_DestinationUHieght}_${OUT/IN}_${CNA/CNB}
and drew it up in an Altium-like set of google slides -- see attached "after" BIO diagrams that represent the susb13 and susb2h34 systems now after the 2026-01-13 rack work.

Oli's going to work on adding this convention to all the actual Altium wiring diagrams, D2300401 for susb13 and D2300383 fr susb2h34.

In in the mean time, I spent some quality time with a label maker and re-labeled all the susb13 cables and labeled all the susb2h34 cables. Note -- for the susb13 system, I didn't move any cables, but since I had to relabel the cables anyways to add the CNA/CNB extension, I just relabeled all the cables. As such, the unchanged susb13's BIO cables now match convention again, where the BO/BI chassis destination U-height is correctly assigned to the cable name.

Pictures attached:
susb13:
    SUS-C5_BIOCables_Labeled.jpg # IO Chassis End in SUS-C5
    SUS-C6_BIOCables_Labeled.jpg # BO/BI Chassis End in SUS-C6

susb2h34:
    SUS-C2_BIOCables_Labeled.jpg # IO Chassis End in SUS-C2
    SUS-C1_BIOCables_Labeled.jpg # BO/BI Chassis End in SUS-C1
Images attached to this report
Non-image files attached to this report
H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:22, Thursday 22 January 2026 (88818)
SUS Model Updates: h1susitmpi

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSB123 into SUSB13 for the ITM PI's, we referenced slides 5 and 7. These changes were svn'd as r34388 and were installed and started last week (88781).

These are the changes we had to make for h1susitmpi:

CDS Parameter Block:
- Changed hostname from h1susb123 to h1susb13
- Removed specific_cpu

Output (before, after):
- Change 20 bit DAC into a 28 bit DAC
- Wire up ITMX and ITMY PI OSEM outputs to their corresponding DAC channels

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H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:21, Thursday 22 January 2026 (88820)
SUS Model Updates: h1susauxb2h34

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSH34 into SUSB13 for SUSAUXB2H34, we referenced slides 25 and 26. These changes were svn'd as r34398 and were installed and started last week (88781).

These are the changes we had to made for h1susauxb2h34 (previously called h1susauxh34):

CDS Parameter Block:
- Changed hostname from h1susauxh34 to h1susauxb2h34
- Removed specific_cpu

Input (before, after):
- Added ADC6 and ADC7
- Added BS block (taken from susauxb123)
- Connected ADC6 and ADC7 to BS block

BS Block (after):
- Connected up ADCs according to slide 26

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H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:20, Thursday 22 January 2026 (88814)
SUS Model Updates: h1susbs

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the movement of the BS from SUSB123 to SUSB2H34, we referenced slides 5, 10, 12, 15, 18, and 21. These changes were svn'd as r34436 and were installed and started last week (88781).

These are the changes we had to make for h1susbs:

CDS Parameter Block:
- Changed dcuid
- Changed hostname from h1susb123 to h1susb2h34
- Removed specific_cpu

Input (before, after):
- Removed ADC1 since now all OSEM channels are on one ADC (called ADC1 in diagrams)
- Redid ADC to OSEM configuration
- Removed ITMX L3 and ITMY L3 channels from SHMEM that came in for ITM L3 BIO
- Added BS BIO channels for each BS stage (coming in from MC2) to SHMEM since the BS BIO is now on the MC2 model
- Redid BIO MON stage inputs into BS block to now read in values from SHMEM
    - MCDIO_2_BSM3 is terminated since current BS block doesnt have an M3 BIO

Output (before, after):
- Changed DACs from multiple 20 bit DACs to one 28 bit DAC
- Lined up outputs to their corresponding DAC channels
- Removed ITMX and ITMY L3 BIO channels that went out to ITMX and ITMY from SHMEM
- Added BS BIO channels for each BS stage (going out to MC2) to SHMEM since BS BIO is now on the MC2 model
- Redid BIO CTRL OUT outputs from BS block to now go out to SHMEM channels
    - BS M3 has a 0 coming in for now since current BS block doesn't have an M3 BIO

Binary I/O (before, after):
- Removed BIO blocks since BS BIO is now happening in the MC2 model

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H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:17, Thursday 22 January 2026 (88816)
SUS Model Updates: h1suspr2

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSH34 into SUSB2H34 for PR2, we referenced slides 8, 10, 14, 15, 20, and 21. These changes were svn'd as r34387 and were installed and started last week (88781).

These are the changes we had to make for h1suspr2:

CDS Parameter Block:
- Changed hostname from h1sush34 to h1susb2h34
- Removed specific_cpu

Output (before, after):
- Changed DACs from multiple 18 bit DACs to one 20 bit DAC and one 28 bit DAC
- Lined up outputs to their corresponding DAC channels

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H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:16, Thursday 22 January 2026 (88817)
SUS Model Updates: h1sussr2

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSH34 into SUSB2H34 for SR2, we referenced slides 8, 10, 14, 15, 20, and 21. These changes were svn'd as r34385 and were installed and started last week (88781).

These are the changes we had to make for h1sussr2:

CDS Parameter Block:
- Changed hostname from h1sush34 to h1susb2h34
- Removed specific_cpu

Input (before, after):
- Changed ADC to OSEM channels for M1 RT and SD

Output (before, after):
- Changed DACs from multiple 18 and 20 bit DACs to one 20 bit DAC and one 28 bit DAC
- Lined up outputs to their corresponding DAC channels

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H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:14, Thursday 22 January 2026 (88815)
SUS Model Updates: h1susmc2

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSH34 into SUSB2H34 for MC2, we referenced slides 8, 10, 14, 15, 20, and 21. These changes were svn'd as r34384 and were installed and started last week (88781).

These are the changes we had to make for h1susmc2:

CDS Parameter Block:
- Changed hostname from h1sush34 to h1susb2h34
- Removed specific_cpu

Input (before, after):
- Removed ADC1 since now all OSEM channels are on ADC0
- Redid ADC to OSEM configuration
- Added BS BIO channels for each BS stage (coming in from BS) to SHMEM since the BS BIO is now on the MC2 model

Output (before, after):
- Changed DACs from multiple 18 bit DACs to one 28 bit DAC
- Lined up outputs to their corresponding DAC channels
- Added BS BIO channels for each BS stage (going out to BS) to SHMEM
- Changed ADC channels going to SR3 oplev in PCIE

Binary I/O (before, after):
- Added BS to BIO ENCODE and DECODE blocks
- Added BIO cards for BS
- Added inputs and outputs to BIO blocks for BS

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H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:11, Thursday 22 January 2026 (88813)
SUS Model Updates: h1susitmy

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSB123 into SUSB13 for ITMY, we referenced slides 5, 7, 12, 13, 18, and 19. These changes were svn'd as r34388 and were installed and started last week (88781).

These are the changes we had to make for h1susitmy:

CDS Parameter Block:
- Changed hostname from h1susb123 to h1susb13
- Removed specific_cpu

Input (before, after):
- Removed ADC1 since now all OSEM channels are on ADC0
- Redid ADC to OSEM configuration
- Removed ITMY L3 BIO channel (coming from BS) from SHMEM
- Added ITMX L3 BIO channel (coming in from ITMX L3) to SHMEM since the L3 BIO is now on the ITMY model

Output (before, after):
- Changed DACs from several 20 bit DACs to two 28 bit DACs
- Lined up outputs to their corresponding DAC channels
- Lined up ESD bias and ESD sum outputs to their corresponding DAC channels
- Removed ITMY L3 BIO channel (that went out to BS) from SHMEM
- Added ITMX L3 BIO channel (that goes out to ITMX) to SHMEM since L3 BIO is now on the ITMY model

Binary I/O (before, after):
- Added ITMX L3 and ITMY L3 BIO inputs and routing into the ITMY_BIO_ENCODE block
- Added the ITMX L3 and ITMY L3 BIO out cards
- Added ITMX L3 and ITMY L3 BIO routing into the ITMY_BIO_DECODE block and outputs
- Removed the HWWD_CONTROL input from the ITMY_BIO_ENCODE block and removed the wire going into it from the ITMY_HWWD_BIN_OUT block since there is no physical cable there

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H1 SUS (CDS)
oli.patane@LIGO.ORG - posted 12:09, Thursday 22 January 2026 (88812)
SUS Model Updates: h1susitmx

Jeff, Oli

We made several updates to multiple SUS simulink models as a continuation of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). Our changes were based on our updated G2301306-v10_PARTII - for the conversion from SUSB123 into SUSB13 for ITMX, we referenced slides 5, 7, 12, 13, 18, and 19. These changes were svn'd as r34388 and were installed and started last week (88781).

These are the changes we had to make for h1susitmx:

CDS Parameter Block:
- Changed hostname from h1susb123 to h1susb13
- Removed specific_cpu

Input (before, after):
- Removed ADC1 since now all OSEM channels are on one ADC (called ADC1 in diagrams)
- Redid ADC to OSEM configuration
- Changed name of SHMEM channel that comes in for ITMX L3 BIO
    - Previously was H1:SUS-ITMX_BIO_L3_MON_SHMEM, now is H1:SUSITMY_2_ITMX_L3_BIOMON_SHMEM

Output (before, after):
- Changed DACs from several 20 bit DACs to two 28 bit DACs
- Lined up outputs to their corresponding DAC channels
- Lined up ESD bias and ESD sum outputs to their corresponding DAC channels
- Changed name of SHMEM channel that goes out for ITMX L3 BIO
    - Previously was H1:SUS-ITMX_BIO_L3_CTRL_SHMEM, now is H1:SUSITMY_2_ITMX_L3_BIOCTRL_SHMEM

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