We set up the new RF source and a spare in the EE shop with the custom 9.100230 MHz OCXOs. These OCXOs have a very small tuning coefficient of 0.2 ppm/V which is about 25 times lower than the others. This effects the gain of the PLL and it takes about an hour to lock (see Timing_XOLocking_lowgain.pdf).

A new revision of the 1PPS locking FPGA code (E1200033-v3, version 3, svn 103) has been released which adds gain selection through the DIP switches. The attached figures show the step response for gains of 4, 16 and 64, respectively (Timing_XOLocking_gain4_step.pdf, Timing_XOLocking_gain16_step.pdf and Timing_XOLocking_gain64_step.pdf). The PLL is still under damped with a gain of 4, but over damped with the gain of 64. With a gain of 16 the RF source locks in about 5 minutes.