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Reports until 15:21, Tuesday 25 August 2015
H1 SUS (SUS, SYS)
leonid.prokhorov@LIGO.ORG - posted 15:21, Tuesday 25 August 2015 (20874)
OPLEV charge measurements
Charge measurements was done on both ETMs.
It seems like ETMY change the sign of charging after changing the bias sign on ETMY (see 20387) while ETMX charging is the same (as well as the bias sign).
Now (since Aug,10) both ETMX and ETMY Biases are -9.5V, 
Plots are in attachment.
Images attached to this report
H1 SYS
hugh.radkins@LIGO.ORG - posted 13:51, Tuesday 25 August 2015 - last comment - 14:46, Tuesday 25 August 2015(20870)
ODC Master model Updated per E1500352

w/conversations and email from Duncan,

Svn Up'd:  userapps/release/sys/common/models/ODC_MASTER_PARTS_V2.mdl

Svn Added:  userapps/release/sys/common/src/RIP_OBS_READY_FROM_MASTER.c

Modified: userapps/release/sys/h1/models/h1odcmaster.mdl from DCC E1500352 tarball.

recompiled, installed, started.

This presented two new channels:  H1:ODC-AUTO_UNSET_OBS_INTENT & H1:ODC-OBS_READY_BIT_NUMBER

These were set to be monitored in SDF and set their values to 1 & 2 respectively.  This means 1==> yes automatically unset the observation intent bit based on the value of bit number 2 in ODC MASTER.

The modified safe.snap has been commited to the svn.

Comments related to this report
jameson.rollins@LIGO.ORG - 14:13, Tuesday 25 August 2015 (20871)

I have updated and reloaded the guardian IFO top node such that it no longer unsets the 'ODC-OPERATOR_OBSERVATION_READY' (aka INTENT) bit after dropping from OK.  This logic is now handled in the ODC MASTER.

Please see LLO alog 19981 for information about how this affects operations.  Probably the most salient aspect of the change:

The INTENT (ODC-OPERATOR_OBSERVATION_READY) bit will not be allowed to be set by the operator unless the READY bit is True.

The READY bit is composed of two parts:

  • guardian IFO top node OK
  • No EXC channels active (as determined by ODC master)

If the INTENT bit can not be set, look at the state of both of these things to determine if there is an issue.

jameson.rollins@LIGO.ORG - 14:46, Tuesday 25 August 2015 (20872)

I also just removed the unsetting of ODC-OPERATOR_OBSERVATION_READY from ISC_LOCK (it shouldn't have been there in the first place).  ISC_LOCK was reloaded, so this change should have taken affect.

H1 TCS
nutsinee.kijbunchoo@LIGO.ORG - posted 13:44, Tuesday 25 August 2015 (20869)
TCS CO2X temp sensor installation

Elli, Nutsinee

The clamp turned out to be a little big so the sensor couldn't be firmly held to the mount but it is in place and won't go anywhere. The configuration is the same as how we installed it at the CO2Y.

H1 PEM
filiberto.clara@LIGO.ORG - posted 13:32, Tuesday 25 August 2015 (20868)
H1 PEM LVEA
Terminated bnc cables for the PEM-CS_RADIO_LVEA antenna. Cables are along west wall of HAM2.
Installed an 18 Bit DAC AI Chassis D1101785 in OAF-C1 rack, slot U22&U21. SN S1201691
Installed an Quad I&Q RF Demodulator D0902796 in OAF-C1 rack, slot U27. SN S1000981
Pulled 2 LMR cables from the OAF-C1 rack to ISC-C4 rack for the demodulator LO signals of 9MHz and 45MHz. The LO signals are connected to the follwing RF Distribution Amplifier units in ISC-C4:
9MHz U26 Port 4
45MHz U19 Port 4

H1 SUS
filiberto.clara@LIGO.ORG - posted 13:07, Tuesday 25 August 2015 (20867)
ETMX UIM Chassis
Replaced breaker on UIM chassis (S0900303) from a 1A to 3A. Nominal current draw with no load is ~0.5 amps. Will monitor to see if this resolves issue. 
H1 SYS
hugh.radkins@LIGO.ORG - posted 12:57, Tuesday 25 August 2015 (20866)
Maintenance Day Time Line

All times local PDT.

0728  IFO Dropped Lock

0755 Richard Starts on PRM -- Finished 1044 -- No obvious problem but Chassis changed.

0759 Hugh Installs STS2-A at HAM2 -- Finished 0825

0822 Keita to EndX for QPD checks-- Finished 1043--No obvious problem.

0833 Phil to EndX for UIM -- Upgraded breaker from 1 to 3Amps.  Done 0935

0835 Hugh updates ODC MASTER for Auto Intent_Bit Reset  ECR E1500352

0855 Ellie to TCS HWS Camera Power Supply, removes filter to EE Shop.  No good, revert to no-filter configuration.  Done 1033

0912 Nutsinee to TCSX for Temperature Sensor install--Finished 1158.

0930 Barker completes LSC/ASC/OAF/PEMEX  Model updates for SciFrame changes & others (see Kawabi=LSC)

1031 Kiwamu doing ALS Diff Electronic Measurements.  Done 1245

1000 SysDiag Guardian node down for rebuild finished 1723

1100 Leo starts ETM Charge Measurements.  Complete 1239.

1105 Model Restarts--H1OAF fails from Epics problem.  Halt model restarts.

1115 JimB fixes Epics problem.  Model Restarts resume.

1124 DAQ Restart

1130 Daniel & Sheila at AS WFS Electronic response  & dark noise  Done 1240.

~1100 Phil Terminating PEM Cables in LVEA and CER.  Installing 18bit DAC card.  Done 1244.

H1 SUS (ISC, SUS, SYS)
richard.mccarthy@LIGO.ORG - posted 12:38, Tuesday 25 August 2015 - last comment - 09:09, Wednesday 26 August 2015(20865)
PRM M3 LL coil investigation
Following up on Evan's investigation into the glitches from LL coil on the PRM M3.   I tried to monitor the output with a scope attached.  I was not looking for very big signals as the the noisemon indicated roughly 30mV signal and it has some gain associated with it. So I connected to scope probes to the LL coil drive signal and looked at it on a scope with a trigger set fairly low.(10s of milivolts).  I also looked at UL just for comparison.   I was able to get the signal to trigger on some events  on LL that were not seen at as high a level on UL.  This was with the DAC both connected and disconnected with small offset (20 counts) applied and a large offset (20,000 counts) applied.  After a couple of hours of investigation I decided there were some glitches present and seemed to be from the coil driver not the DAC.  I also looked at the DAC input to the coil driver and did not see the glitches.  In the end I swapped out the coil driver.  I am not 100% certain this will fix the problem as it was difficult to verify the glitches were present at all times.

Comments related to this report
filiberto.clara@LIGO.ORG - 09:09, Wednesday 26 August 2015 (20914)
Unit removed S1100045.
Unit installed S1100025.
H1 ISC
keita.kawabe@LIGO.ORG - posted 11:49, Tuesday 25 August 2015 (20864)
LSC and ASC science frame channels update

WP5452: New LSC and ASC models were made and built yesterday, and were installed today. ASC update also include one bug fix for ASC ODC (change one data type from cdsepicsout to cdsepicslong).

As for LSC, as per E1500343, 45MHz AM monitor channels was added to the science frame at 16kHz.

As for ASC, as per E1500348, input side of ASC feedback filters were added to ASC at 256Hz, and as per E1500349, ALS-C_TRX_A_LF_OUT_DQ and ALS-C_TRY_A_LF_OUT_DQ (both 2k) were removed.

After the installation, in chans/daq directory, LSC and ASC science frame channels were checked.

$ grep -B 1 "^acquire=3" H1LSC.ini|grep DQ

[H1:IMC-F_OUT_DQ]
[H1:IMC-I_OUT_DQ]
[H1:IMC-L_OUT_DQ]
[H1:IMC-REFL_DC_OUT_DQ]
[H1:IMC-TRANS_OUT_DQ]
[H1:LSC-ASAIR_B_RF90_I_ERR_DQ]
[H1:LSC-MCL_IN1_DQ]
[H1:LSC-MCL_OUT_DQ]
[H1:LSC-MICH_IN1_DQ]
[H1:LSC-MICH_OUT_DQ]
[H1:LSC-MOD_RF45_AM_AC_OUT_DQ]
[H1:LSC-ODC_CHANNEL_OUT_DQ]
[H1:LSC-POPAIR_B_RF18_I_ERR_DQ]
[H1:LSC-POPAIR_B_RF90_I_ERR_DQ]
[H1:LSC-POP_A_LF_OUT_DQ]
[H1:LSC-POP_A_RF45_I_ERR_DQ]
[H1:LSC-POP_A_RF45_Q_ERR_DQ]
[H1:LSC-POP_A_RF9_I_ERR_DQ]
[H1:LSC-POP_A_RF9_Q_ERR_DQ]
[H1:LSC-PRCL_IN1_DQ]
[H1:LSC-PRCL_OUT_DQ]
[H1:LSC-REFL_A_LF_OUT_DQ]
[H1:LSC-REFL_A_RF45_I_ERR_DQ]
[H1:LSC-REFL_A_RF45_Q_ERR_DQ]
[H1:LSC-REFL_A_RF9_I_ERR_DQ]
[H1:LSC-REFL_A_RF9_Q_ERR_DQ]
[H1:LSC-REFL_SERVO_ERR_OUT_DQ]
[H1:LSC-REFL_SERVO_SLOW_OUT_DQ]
[H1:LSC-SRCL_IN1_DQ]
[H1:LSC-SRCL_OUT_DQ]

 

$ grep -B 1 "^acquire=3" H1ASC.ini|grep DQ

[H1:ASC-AS_A_DC_PIT_OUT_DQ]
[H1:ASC-AS_A_DC_SUM_OUT_DQ]
[H1:ASC-AS_A_DC_YAW_OUT_DQ]
[H1:ASC-AS_A_RF36_I_PIT_OUT_DQ]
[H1:ASC-AS_A_RF36_I_YAW_OUT_DQ]
[H1:ASC-AS_A_RF36_Q_PIT_OUT_DQ]
[H1:ASC-AS_A_RF36_Q_YAW_OUT_DQ]
[H1:ASC-AS_A_RF45_I_PIT_OUT_DQ]
[H1:ASC-AS_A_RF45_I_YAW_OUT_DQ]
[H1:ASC-AS_A_RF45_Q_PIT_OUT_DQ]
[H1:ASC-AS_A_RF45_Q_YAW_OUT_DQ]
[H1:ASC-AS_B_DC_PIT_OUT_DQ]
[H1:ASC-AS_B_DC_SUM_OUT_DQ]
[H1:ASC-AS_B_DC_YAW_OUT_DQ]
[H1:ASC-AS_B_RF36_I_PIT_OUT_DQ]
[H1:ASC-AS_B_RF36_I_YAW_OUT_DQ]
[H1:ASC-AS_B_RF36_Q_PIT_OUT_DQ]
[H1:ASC-AS_B_RF36_Q_YAW_OUT_DQ]
[H1:ASC-AS_B_RF45_I_PIT_OUT_DQ]
[H1:ASC-AS_B_RF45_I_YAW_OUT_DQ]
[H1:ASC-AS_B_RF45_Q_PIT_OUT_DQ]
[H1:ASC-AS_B_RF45_Q_YAW_OUT_DQ]
[H1:ASC-AS_C_PIT_OUT_DQ]
[H1:ASC-AS_C_SUM_OUT_DQ]
[H1:ASC-AS_C_YAW_OUT_DQ]
[H1:ASC-CHARD_P_IN1_DQ]
[H1:ASC-CHARD_P_OUT_DQ]
[H1:ASC-CHARD_Y_IN1_DQ]
[H1:ASC-CHARD_Y_OUT_DQ]
[H1:ASC-CSOFT_P_IN1_DQ]
[H1:ASC-CSOFT_P_OUT_DQ]
[H1:ASC-CSOFT_Y_IN1_DQ]
[H1:ASC-CSOFT_Y_OUT_DQ]
[H1:ASC-DC1_P_IN1_DQ]
[H1:ASC-DC1_P_OUT_DQ]
[H1:ASC-DC1_Y_IN1_DQ]
[H1:ASC-DC1_Y_OUT_DQ]
[H1:ASC-DC2_P_IN1_DQ]
[H1:ASC-DC2_P_OUT_DQ]
[H1:ASC-DC2_Y_IN1_DQ]
[H1:ASC-DC2_Y_OUT_DQ]
[H1:ASC-DC3_P_IN1_DQ]
[H1:ASC-DC3_P_OUT_DQ]
[H1:ASC-DC3_Y_IN1_DQ]
[H1:ASC-DC3_Y_OUT_DQ]
[H1:ASC-DC4_P_IN1_DQ]
[H1:ASC-DC4_P_OUT_DQ]
[H1:ASC-DC4_Y_IN1_DQ]
[H1:ASC-DC4_Y_OUT_DQ]
[H1:ASC-DC5_P_IN1_DQ]
[H1:ASC-DC5_P_OUT_DQ]
[H1:ASC-DC5_Y_IN1_DQ]
[H1:ASC-DC5_Y_OUT_DQ]
[H1:ASC-DHARD_P_IN1_DQ]
[H1:ASC-DHARD_P_OUT_DQ]
[H1:ASC-DHARD_Y_IN1_DQ]
[H1:ASC-DHARD_Y_OUT_DQ]
[H1:ASC-DSOFT_P_IN1_DQ]
[H1:ASC-DSOFT_P_OUT_DQ]
[H1:ASC-DSOFT_Y_IN1_DQ]
[H1:ASC-DSOFT_Y_OUT_DQ]
[H1:ASC-INP1_P_IN1_DQ]
[H1:ASC-INP1_P_OUT_DQ]
[H1:ASC-INP1_Y_IN1_DQ]
[H1:ASC-INP1_Y_OUT_DQ]
[H1:ASC-INP2_P_IN1_DQ]
[H1:ASC-INP2_P_OUT_DQ]
[H1:ASC-INP2_Y_IN1_DQ]
[H1:ASC-INP2_Y_OUT_DQ]
[H1:ASC-MICH_P_IN1_DQ]
[H1:ASC-MICH_P_OUT_DQ]
[H1:ASC-MICH_Y_IN1_DQ]
[H1:ASC-MICH_Y_OUT_DQ]
[H1:ASC-ODC_CHANNEL_OUT_DQ]
[H1:ASC-OMC_A_PIT_OUT_DQ]
[H1:ASC-OMC_A_SUM_OUT_DQ]
[H1:ASC-OMC_A_YAW_OUT_DQ]
[H1:ASC-OMC_B_PIT_OUT_DQ]
[H1:ASC-OMC_B_SUM_OUT_DQ]
[H1:ASC-OMC_B_YAW_OUT_DQ]
[H1:ASC-POP_A_PIT_OUT_DQ]
[H1:ASC-POP_A_SUM_OUT_DQ]
[H1:ASC-POP_A_YAW_OUT_DQ]
[H1:ASC-POP_B_PIT_OUT_DQ]
[H1:ASC-POP_B_SUM_OUT_DQ]
[H1:ASC-POP_B_YAW_OUT_DQ]
[H1:ASC-POP_X_RF_I_PIT_OUT_DQ]
[H1:ASC-POP_X_RF_I_YAW_OUT_DQ]
[H1:ASC-POP_X_RF_Q_PIT_OUT_DQ]
[H1:ASC-POP_X_RF_Q_YAW_OUT_DQ]
[H1:ASC-PRC1_P_IN1_DQ]
[H1:ASC-PRC1_P_OUT_DQ]
[H1:ASC-PRC1_Y_IN1_DQ]
[H1:ASC-PRC1_Y_OUT_DQ]
[H1:ASC-PRC2_P_IN1_DQ]
[H1:ASC-PRC2_P_OUT_DQ]
[H1:ASC-PRC2_Y_IN1_DQ]
[H1:ASC-PRC2_Y_OUT_DQ]
[H1:ASC-REFL_A_DC_PIT_OUT_DQ]
[H1:ASC-REFL_A_DC_SUM_OUT_DQ]
[H1:ASC-REFL_A_DC_YAW_OUT_DQ]
[H1:ASC-REFL_A_RF45_I_PIT_OUT_DQ]
[H1:ASC-REFL_A_RF45_I_YAW_OUT_DQ]
[H1:ASC-REFL_A_RF45_Q_PIT_OUT_DQ]
[H1:ASC-REFL_A_RF45_Q_YAW_OUT_DQ]
[H1:ASC-REFL_A_RF9_I_PIT_OUT_DQ]
[H1:ASC-REFL_A_RF9_I_YAW_OUT_DQ]
[H1:ASC-REFL_A_RF9_Q_PIT_OUT_DQ]
[H1:ASC-REFL_A_RF9_Q_YAW_OUT_DQ]
[H1:ASC-REFL_B_DC_PIT_OUT_DQ]
[H1:ASC-REFL_B_DC_SUM_OUT_DQ]
[H1:ASC-REFL_B_DC_YAW_OUT_DQ]
[H1:ASC-REFL_B_RF45_I_PIT_OUT_DQ]
[H1:ASC-REFL_B_RF45_I_YAW_OUT_DQ]
[H1:ASC-REFL_B_RF45_Q_PIT_OUT_DQ]
[H1:ASC-REFL_B_RF45_Q_YAW_OUT_DQ]
[H1:ASC-REFL_B_RF9_I_PIT_OUT_DQ]
[H1:ASC-REFL_B_RF9_I_YAW_OUT_DQ]
[H1:ASC-REFL_B_RF9_Q_PIT_OUT_DQ]
[H1:ASC-REFL_B_RF9_Q_YAW_OUT_DQ]
[H1:ASC-SRC1_P_IN1_DQ]
[H1:ASC-SRC1_P_OUT_DQ]
[H1:ASC-SRC1_Y_IN1_DQ]
[H1:ASC-SRC1_Y_OUT_DQ]
[H1:ASC-SRC2_P_IN1_DQ]
[H1:ASC-SRC2_P_OUT_DQ]
[H1:ASC-SRC2_Y_IN1_DQ]
[H1:ASC-SRC2_Y_OUT_DQ]
 

H1 TCS
eleanor.king@LIGO.ORG - posted 11:12, Tuesday 25 August 2015 (20863)
Filter module removed from ITM HWS power supply

Filiberto, Elli 

The ITM HWS weren't working properly after installing the filter box last week (alog 20626).   Power goes from the HWS breakout box through the filter module to the HWS cameras.  The voltage drop across the filter put the voltage at the cameras below their operating range.  (There is 14V at breakout box output, 10.8V after the filter.  Operating voltage of the camera is 12-15V.  13.3V reaches camera with no filter installed.)  We have taken the filter out and reverted to the previous HWS configuration.  We will rethink the choice of filter.

H1 GRD
jameson.rollins@LIGO.ORG - posted 10:58, Tuesday 25 August 2015 (20862)
New guardian diagnostic infrastructure installed, SYS_DIAG node renamed to DIAG_MAIN

The new SYS_DIAG infrastructure for the Guardian diagnostic nodes has been installed.  The new infrastructure allows for multiple diagnostic nodes with different names.

The old SYS_DIAG node was re-written to use the new infrastructure, and was renamed as DIAG_MAIN:

$USERAPPS/sys/h1/guardian/DIAG_MAIN.py

The old SYS_DIAG node was destroyed, and DIAG_MAIN was created and started.  DIAG_MAIN is now running and appears to be executing all tests normally.

A DAQ restart is required to pull in the new DIAG_MAIN channels.

Usage of SYS_DIAG for diagnostic guardian nodes

The main infrastructure for SYS_DIAG is encoded in the SYS_DIAG module:

$USERAPPS/sys/common/guardian/SYS_DIAG.py

DO NOT MODIFY THE SYS_DIAG MODULE.  This module defines common infrastructure for loading and running the tests.

To create a new diagnostic node, define a new module: $USERAPPS/sys//guardian/DIAG_.  This module should import everything from SYS_DIAG, and define all diagnostic tests as follows:

from SYS_DIAG import *

@SYSDIAG.register
def TEST_SOMETHING()
    """One-line description of test.

    Other info about test.

    """
   if some_condition():
        yield "message to be reported to operator"

Note the "@SYSDIAG.register" decorator above the TEST_SOMETHING function.  That's what registers the function as a diagnostic test that gets run in the RUN_TESTS state (see below).  The module can define as many functions as you like, but only those registered will be run as diagnostic tests.

Also note that the function "yields" a diagnostic message.  Each test can define as many conditions as you like, and for each failing condition, yield a diagnostic message as show above.  The yielded message will be displayed as a NOTIFICATION by the DIAG guardian node, tagged with the test from whence it came.

The DIAG module only needs to define tests as described above, and should not define any GuardState classes. The states are imported from SYS_DIAG: INIT that just lists the registered tests, and RUN_TESTS which runs all tests tagged with the @SYSDIAG.register decorator.

Tests can be defined in separate modules and imported as needed in the usual way.

H1 ISC
stefan.ballmer@LIGO.ORG - posted 10:39, Tuesday 25 August 2015 (20860)
power cycled EX QPD interface and whitening
(Keita writing)
Nothing changed for green, it's hard to tell if anything happened for IR as there's no light right now.

Analog signal coming out of the interface looked OK in that no high frequency oscillation was observed in green as well as IR. Ditto for Analog signal coming out of whitening.

I didn't pull the QPD interface chassis out, as one of the clean room legs is blocking the front side of the ISC field rack and I couldn't move the clean room on my own.
H1 SYS
daniel.sigg@LIGO.ORG - posted 09:19, Tuesday 25 August 2015 (20859)
EtherCAT software subversion numbers

Here is a quick script to get the svn numbers of the TwinCAT PLCs:

#!/bin/csh
ezcaread ${1}:SYS-ETHERCAT_C1PLC1_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_C1PLC2_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_C1PLC3_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_X1PLC1_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_X1PLC2_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_X1PLC3_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_Y1PLC1_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_Y1PLC2_SVNREVISION
ezcaread ${1}:SYS-ETHERCAT_Y1PLC3_SVNREVISION

and here are the results:

H1:SYS-ETHERCAT_C1PLC1_SVNREVISION = 2406
H1:SYS-ETHERCAT_C1PLC2_SVNREVISION = 2402
H1:SYS-ETHERCAT_C1PLC3_SVNREVISION = 2402
H1:SYS-ETHERCAT_X1PLC1_SVNREVISION = 2357
H1:SYS-ETHERCAT_X1PLC2_SVNREVISION = 2357
H1:SYS-ETHERCAT_X1PLC3_SVNREVISION = 2357
H1:SYS-ETHERCAT_Y1PLC1_SVNREVISION = 2357
H1:SYS-ETHERCAT_Y1PLC2_SVNREVISION = 2325
H1:SYS-ETHERCAT_Y1PLC3_SVNREVISION = 2325

These are the most recent versions for the respective PLCs.

H1 SYS
hugh.radkins@LIGO.ORG - posted 09:09, Tuesday 25 August 2015 (20857)
Maintenance Day Beginnings

At 0728 pdt the IFO dropped lock.

Prior to that the SDF was green except for the OMC, SUSETMY, and SUSPRM.  Some CALC stuff too but I'll not worry about that.

The PRM diffs are from the LL Coil driver changes and the OMC & SUSETMY diffs are captured below.  These system should not have to be restarted today.

As of 0905,

The STS2-A is installed.

Richard has been and continues to work on the PRM coils.

Keita is working the EndX QPD.

Phil is working the ETMX UIM Breaker and

Ellie is working on the TCS HWS Camera Power Supply.

Images attached to this report
H1 General
edmond.merilh@LIGO.ORG - posted 07:50, Tuesday 25 August 2015 - last comment - 10:25, Tuesday 25 August 2015(20856)
End of Shift Summary and Lock Log - Owl

ALL TIMES IN UTC

 

Summary:

H1 remained locked for ~6+ hours. LLO went down at 12:39UTC according to Doug Lormand’s aLog. There was ~4hrs coincidental lock with LLO. Wind and Seismic still calm. ETMY glitches at 10:12, 10:24, 11:12, 11:55, 13:19, 13:35, 14:27. Handing off to Jeff B.

 

LOCK LOG:

Comments related to this report
hang.yu@LIGO.ORG - 10:25, Tuesday 25 August 2015 (20858)

A plot of lockloss at 14:27:29 UTC is attached.

ASC-POP glitched ~16s before and ASC-PRC2 starts to oscillating at about the same time ( and the oscillation became really huge about ~ 6s before lockloss). They were both high frequency (>128 Hz). 

Stefan also looked at the ODC channels yet did not find a clear clue about what might be the cause of this event. https://ldvw.ligo.caltech.edu/ldvw/view?act=doplot&baseSelector=true&Raw_28064=Raw.+&Minute-trend_28064=none&Second-trend_28064=none&Raw_228578=Raw.+&Minute-trend_228578=none&Second-trend_228578=none&Raw_220848=Raw.+&Minute-trend_220848=none&Second-trend_220848=none&Raw_228580=Raw.+&Minute-trend_228580=none&Second-trend_228580=none&strtTime=1124548064&strtTime=&strtTime=&strtTime=&strtTime=&duration=3&repeatDur=0&repeatUnit=seconds&rptCnt=1&plotGroup=time&gwts_hpfilt=&gwts_xmin=&gwts_xmax=&gwts_epoch=&gwts_ymin=&gwts_ymax=&gwsp_secpfft=&gwsp_ovlap=&gwsp_hpfilt=&gwsp_fmin=&gwsp_fmax=&gwsp_ymin=&gwsp_ymax=&spg_window=Hanning&spg_scaling=ASD&spg_secperfft=1&spg_fftoverlap=&spg_fmin=&spg_fmax=&spg_lo=0.2&spg_up=1.0&spg_color=Jet&gwspgm_secpfft=&gwspgm_ovlap=&gwspgm_epoch=&gwspgm_hpfilt=&gwspgm_fmin=&gwspgm_fmax=&gwspgm_ymin=&gwspgm_ymax=&gwspgm_imin=&gwspgm_imax=&gwcoh_refchan=H1%3AASC-ODC_CHANNEL_OUT_DQ&gwcoh_secpfft=&gwcoh_ovlap=&gwcoh_hpfilt=&gwcoh_fmin=&gwcoh_fmax=&gwcoh_ymin=&gwcoh_ymax=&gwcohgm_refchan=H1%3AASC-ODC_CHANNEL_OUT_DQ&gwcohgm_secpfft=&gwcohgm_ovlap=&gwcohgm_epoch=&gwcohgm_hpfilt=&gwcohgm_fmin=&gwcohgm_fmax=&gwcohgm_ymin=&gwcohgm_ymax=&gwcohgm_imin=&gwcohgm_imax=&wplt_plttyp=spectrogram_whitened&wplt_plttimes=1.00+4.00+16.00+32.00&wplt_smplfrq=2048&wplt_pltfrq=0+inf&wplt_pltenergyrange=0.0+25.5&wplt_srchtime=64&wplt_srchfrqrng=0+inf&wplt_srchqrng=4.0+64.0&blrms_fupper=&blrms_flower=&blrms_stride=&doOdc=Generate+ODC+Plots%3Cbr%3E%3Cbr%3E&ts_timeaxis=%26%23916%3Bt&ts_linethickness=2&window=Hanning&scaling=Amplitude+spectral+density&sp_linethickness=2&secperfft=1.0&fftoverlap=0.5&fmin=&fmax=&sp_logx=Freq+axis+logarithmic&sp_logy=Range+axis+logarithmic&sp_newplt=Use+new+plot+functions&coh_scaling=Linear&coh_linethickness=2&coh_secperfft=1&coh_fftoverlap=&coh_fmin=&coh_fmax=&coh_refchan=H1%3AASC-ODC_CHANNEL_OUT_DQ&plotSize=Default+%281200x600%29&plot=Plot+%BB&dwnFmt=LigoDV+export

Besides, the ground motion did not seemed to be related to this lockloss as indicated by the second plot.

Images attached to this comment
H1 General
edmond.merilh@LIGO.ORG - posted 04:34, Tuesday 25 August 2015 (20855)
Mid-Shift Update: OWL

ALL TIMES IN UTC

 

Upon Arrival: IFO not locked. Calibration going on. Wind calm. Seismic calm

Summary:

Wind and seismic remain calm. IFO has been locked and in Undisturbed/Observing Mode since 9:37UTC @ ~66Mpc. A few ETMY glitches, nothing major. Everything looks good so far.

Activity Log: Not much activity. Folks here from the day eventually left.
H1 SUS
jeffrey.kissel@LIGO.ORG - posted 23:07, Monday 24 August 2015 - last comment - 02:29, Wednesday 26 August 2015(20848)
QUAD Overview Screen Rocker Switch Death Bug Fixed
J. Kissel, P. Thomas

Given that we've had so many examples of rocker switch death this evening (see LHO aLOG 20839), I was able to identify that my new(ish) warning message about this failure mode on the MEDM overview screen (see LHO aLOG 20281) had a bug. The MEDM logic was watching L2 for all three stages, L2, L1, and M0. I've committed the bug-fix to the SVN such that LLO can receive its benefits.
Comments related to this report
corey.gray@LIGO.ORG - 10:47, Tuesday 25 August 2015 (20861)

What is the MEDM Overview Screen?  Is this the overall QUAD Overview?  If so, where is the new(ish) warning message?  Are you talking about the Guardian message window (upper right corner) on the QUAD overview?

evan.hall@LIGO.ORG - 02:29, Wednesday 26 August 2015 (20899)

On the top-level screen for each quad, you should see a red rectangle appear around the top, UIM, or PUM coil output filters that says "rocker switch death", as in this screenshot from Jeff's alog.

H1 CAL (ISC)
jeffrey.kissel@LIGO.ORG - posted 16:37, Monday 24 August 2015 - last comment - 02:51, Tuesday 25 August 2015(20833)
QUAD PUM Driver State Changed to LP ON, ACQ OFF (State 3)
J. Kissel, S. Dwyer, E. Hall

As I was about to characterizing the ETMY coil drivers (i.e. the UIM and PUM), I noticed that they were in their highest noise state. After conversations with Sheila and Evan, we (re)agreed that the PUMs should be run in their lowest noise state, which is with  LP ON and ACQ OFF, or State 3 from T1100507. As such, we've switched all QUADs to this state, and confirmed that ISC_LOCK guardian will ensure this to be true in the future (again). That guardian has been reloaded.

The reason they had been put back into high range (and taken out of the guardian) was that the range was needed to better damp the QUAD roll modes after they had been severely rung up in the Christmas Episode in early August. 

From a calibration stand point, this will affect the DARM calibration by a small amount, but I had not started characterizing the ETMY PUM drivers before I got started, and I'm now full aware of it, so it's affect will be fully understood and expected. As such, we're OK with this configuration change. Further, we'll all be happy with the little bit extra range we get from it (Evan will post an aLOG making a noise statement later)!
Comments related to this report
evan.hall@LIGO.ORG - 02:51, Tuesday 25 August 2015 (20854)

We can hear saturations on the quads during CARM offset reduction and when powering up, but I suppose that's the price we pay for the improved noise performance. [See attachment—blue is from yesterday (coils in high-range), red is from today (coils low range). I can't really claim that the improvements at 70+ Hz are from the coil switching, though.]

We would like to acquire with high range and then switch to low noise at some point during the lock, but the transients unlock the interferometer most of the time. Jeff suggests that we commission the digital switching delays. Perhaps that can be done parasitically with calibration activities.

Images attached to this comment
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